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1. 发明授权

US08768998B1 Compact switched-capacitor FIR filter implementation 有权
标题翻译：紧凑型开关电容FIR滤波器实现
公开(公告)号：US08768998B1
公开(公告)日：2014-07-01
申请号：US13291715
申请日：2011-11-08
申请人： Uday Dasgupta , Qing Chen
发明人： Uday Dasgupta , Qing Chen
IPC分类号： G06G7/02
CPC分类号： H03H15/00 , H03H19/004
摘要： A system is provided to perform non-recursive signal processing using a sampled data technique and a parallel network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals to obtain analog-valued samples. These samples are collected into data blocks that are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using the parallel network to produce a processed analog output signal. Each individual processing path of the parallel network processes a specific data block of the set of data blocks. The number of parallel processing paths is the same as one plus the degree of the polynomial representing the desired or overall input/output equation characterizing the non-recursive signal processing.
摘要翻译：提供了一种使用采样数据技术和开关电容滤波器的并联网络执行非递归信号处理的系统。以规则的时间间隔以时间顺序对输入的模拟信号进行采样，以获得模拟值采样。这些样本被收集到被组装成一组数据块的数据块中。属于一组数据块的连续数据块与第一数据块部分重叠。使用并行网络基本上同时对所述集合的所有数据块执行非递归信号处理，以产生经处理的模拟输出信号。并行网络的每个单独处理路径处理该组数据块的特定数据块。并行处理路径的数量与一个加上代表表征非递归信号处理的期望或总体输入/输出方程的多项式的程度相同。

2. 发明授权

US08073894B1 Compact switched-capacitor FIR filter implementation 有权
标题翻译：紧凑型开关电容FIR滤波器实现
公开(公告)号：US08073894B1
公开(公告)日：2011-12-06
申请号：US11935815
申请日：2007-11-06
申请人： Uday Dasgupta , Qing Chen
发明人： Uday Dasgupta , Qing Chen
IPC分类号： G06G7/02
CPC分类号： H03H15/00 , H03H19/004
摘要： A system is provided to perform non-recursive signal processing tasks using a sampled data technique and a network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals in order to obtain analog-valued samples. These samples are collected into data blocks and the data blocks are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using a parallel network of switched capacitor filters, in order to produce a processed analog output signal. Each individual processing path of the parallel network of switched capacitor filters processes a specific data block of the set of data blocks. The number of parallel processing paths is the same as one plus the degree of the polynomial representing the desired or overall input/output equation characterizing the non-recursive signal processing. An implementing architecture can be simplified by factorizing the polynomial representing the input/output equation into smaller sized polynomial sub-tasks that can each be implemented by a sub-system of parallel network of switched capacitor filters of smaller complexity.
摘要翻译：提供了一种使用采样数据技术和开关电容滤波器网络执行非递归信号处理任务的系统。为了获得模拟值样本，输入模拟信号以时间顺序方式以规则的时间间隔进行采样。将这些样本收集到数据块中，并将数据块组装成一组数据块。属于一组数据块的连续数据块与第一数据块部分重叠。使用开关电容滤波器的并联网络，基本上同时对所述集合的所有数据块执行非递归信号处理，以便产生经处理的模拟输出信号。开关电容滤波器的并联网络的每个单独处理路径处理该组数据块的特定数据块。并行处理路径的数量与一个加上代表表征非递归信号处理的期望或总体输入/输出方程的多项式的程度相同。可以通过将表示输入/输出方程的多项式分解为更小尺寸的多项式子任务来简化实现架构，其可以分别由较小复杂度的开关电容器滤波器的并联网络的子系统来实现。

3. 发明申请

US20100066449A1 THREE-STAGE FREQUENCY-COMPENSATED OPERATIONAL AMPLIFIER FOR DRIVING LARGE CAPACITIVE LOADS 有权
标题翻译：用于驱动大容量负载的三级频率补偿运算放大器
公开(公告)号：US20100066449A1
公开(公告)日：2010-03-18
申请号：US12486759
申请日：2009-06-18
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/086 , H03F2200/153 , H03F2200/45 , H03F2203/45632 , H03F2203/45674
摘要： A three-stage frequency-compensated operational amplifier includes a first-stage circuit, a second-stage circuit incorporated with a first compensation circuit, a third-stage circuit, and a second compensation circuit. The three-stage frequency-compensated operational amplifier functions as a two-stage operational amplifier at high frequencies, thereby capable of driving large capacitive loads with low power consumption.
摘要翻译：三级频率补偿运算放大器包括第一级电路，并入有第一补偿电路的第二级电路，第三级电路和第二补偿电路。三级频率补偿运算放大器在高频下用作两级运算放大器，从而能够以低功耗驱动大容量负载。

4. 发明申请

US20100066320A1 Integrated LDO with Variable Resistive Load 有权
标题翻译：具有可变电阻负载的集成LDO
公开(公告)号：US20100066320A1
公开(公告)日：2010-03-18
申请号：US12542720
申请日：2009-08-18
申请人： Uday Dasgupta , Alexander Tanzil
发明人： Uday Dasgupta , Alexander Tanzil
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G05F1/575
摘要： To provide adequate compensation for a wide range of output loads, a low dropout (LDO) regulator has an amplifier, a pass transistor, a voltage divider, a compensation network, and a control circuit. The amplifier outputs a comparison result according to a reference signal and a feedback signal. The pass transistor generates an output current based on the comparison result of the amplifier. The voltage divider generates the feedback signal according to the output current. The compensation network couples the output of the pass transistor to a low-impedance node of the amplifier, and has a compensation capacitor and a variable resistor coupled to the compensation capacitor. The control circuit is coupled to the input of the pass transistor and to the variable resistor for controlling resistance of the variable resistor according to the output current of the pass transistor.
摘要翻译：为了对宽范围的输出负载提供足够的补偿，低压差（LDO）调节器具有放大器，传输晶体管，分压器，补偿网络和控制电路。放大器根据参考信号和反馈信号输出比较结果。传输晶体管根据放大器的比较结果产生输出电流。分压器根据输出电流产生反馈信号。补偿网络将传输晶体管的输出耦合到放大器的低阻抗节点，并具有耦合到补偿电容器的补偿电容器和可变电阻器。控制电路耦合到传输晶体管的输入端和可变电阻器，用于根据传输晶体管的输出电流控制可变电阻器的电阻。

5. 发明授权

US07646247B2 Ahuja compensation circuit for operational amplifier 有权
标题翻译： Ahuja运算放大器补偿电路
公开(公告)号：US07646247B2
公开(公告)日：2010-01-12
申请号：US12131902
申请日：2008-06-02
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F1/14
CPC分类号： H03F1/42 , H03F1/14 , H03F3/3022 , H03F3/45183 , H03F3/45475 , H03F2200/297
摘要： A frequency compensated operational amplifier includes: an input stage, for receiving an input signal; an output stage, coupled to the input stage, for generating an output signal according to an output of the input stage; a first current source, for providing a first bias current; a second current source, for providing a second bias current identical to the first bias current; an Ahuja compensation circuit, comprising: a matched transistor pair, coupled to the first current source and the second current source; a capacitor coupled between the matched transistor pair and the output stage; and a transconductance boosting circuit, coupled to the matched transistor pair, for boosting transconductance of the matched transistor pair.
摘要翻译：频率补偿运算放大器包括：输入级，用于接收输入信号; 输出级，耦合到输入级，用于根据输入级的输出产生输出信号; 用于提供第一偏置电流的第一电流源; 第二电流源，用于提供与第一偏置电流相同的第二偏置电流; Ahuja补偿电路，包括：耦合到第一电流源和第二电流源的匹配晶体管对; 耦合在匹配晶体管对和输出级之间的电容器; 以及耦合到匹配晶体管对的跨导升压电路，用于升高匹配晶体管对的跨导。

6. 发明授权

US07548047B1 Pulse width modulated buck voltage regulator with stable feedback control loop 有权
标题翻译：具有稳定反馈控制回路的脉宽调制降压稳压器
公开(公告)号：US07548047B1
公开(公告)日：2009-06-16
申请号：US11293319
申请日：2005-12-01
申请人： Uday Dasgupta , Rudy Kurniawan , Yayue Zhang
发明人： Uday Dasgupta , Rudy Kurniawan , Yayue Zhang
IPC分类号： G05F1/00
CPC分类号： H02M3/156
摘要： A pulse-width modulated buck regulator includes a feedback control without having any external frequency compensation components to stabilize the feedback control loop irrespective of the reactive component of its load impedance. Additionally, the output voltage is maintained constant not only with feedback but also using a power supply voltage compensation scheme. Thus, the feedback control compensates for resistive losses, thus minimizing hardware. The output voltage is compared with first and second reference voltages. If the output voltage is greater than the first reference voltage, a counter's count is decremented. If the output voltage is less than the second reference voltage, the counter's count is incremented. The counter is disabled if the output voltage is smaller than the first reference voltage and greater than the second reference voltage. The duty cycle of the output voltage is varied in accordance with the counter's count.
摘要翻译：脉冲宽度调制降压调节器包括反馈控制，而不用任何外部频率补偿分量来稳定反馈控制回路，而不管其负载阻抗的无功分量如何。此外，输出电压不仅通过反馈保持恒定，而且还使用电源电压补偿方案。因此，反馈控制补偿电阻损耗，从而最小化硬件。将输出电压与第一和第二参考电压进行比较。如果输出电压大于第一个参考电压，则计数器的计数递减。如果输出电压小于第二参考电压，则计数器的计数值递增。如果输出电压小于第一参考电压并大于第二参考电压，计数器将被禁止。输出电压的占空比根据计数器的数量而变化。

7. 发明授权

US06664843B2 General-purpose temperature compensating current master-bias circuit 失效
公开(公告)号：US06664843B2
公开(公告)日：2003-12-16
申请号：US09999001
申请日：2001-10-24
申请人： Uday Dasgupta , Wooi Gan Yeoh
发明人： Uday Dasgupta , Wooi Gan Yeoh
IPC分类号： H01L3500
CPC分类号： G05F3/30 , G05F3/245
摘要： A temperature compensating biasing circuit is constructed by first determining a piecewise function substantially describing a required bias current with respect to temperature. Reference signals are created such that each reference signal describes an amount of contributing currents that, when summed together, generate a master biasing current. The biasing current generator is further constructed to create a thermal signal indicating an operating temperature. Each of the reference signals is compared to the thermal signal. The biasing current generator then identifies which of the contributing currents or portions of the contributing currents are being included to generate the master biasing current. The identified contributing currents and the portions of the contributing currents are then summed to form the master biasing current. The master biasing current may be mirrored to form bias currents that have the temperature compensation bias function.

8. 发明授权

US06298466B1 Method and system for synthesizing operational amplifiers for amplifying systems with minimal total harmonic distortion 失效
标题翻译：用于合成放大系统的运算放大器的方法和系统，具有最小的总谐波失真
公开(公告)号：US06298466B1
公开(公告)日：2001-10-02
申请号：US09206747
申请日：1998-12-07
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： G06F1750
CPC分类号： H03F1/342 , H03F1/086
摘要： A method and system for designing a two-stage operational amplifier having low total harmonic distortion. The method begins with estimating a gain level of a second stage of the operational amplifier. Then a transconductance of the second stage is calculated. A unity gain frequency level for the first stage is calculated and from that the one kilohertz gain level of the first stage. The gain level at one kilohertz is then calculated and from this, the unity gain frequency for the operational amplifier is then calculated. A value of the compensation capacitor for said operational amplifier is calculated followed by calculating a transconductance of a first stage of the operational amplifier. The overall D.C. gain level and the output resistance of the first stage of the operational amplifier is then determined. The transconductance of the first and second stages, the output resistance of the first stage with the load capacitance and resistance will be used to synthesize transistor sizes and bias current levels of the operational amplifier. The design is then simulated for stability and the method is repeated until stability is achieved.
摘要翻译：一种用于设计具有低总谐波失真的两级运算放大器的方法和系统。该方法开始于估计运算放大器的第二级的增益电平。然后计算第二阶段的跨导。计算第一级的单位增益频率电平，并从第一级的1千赫增益电平计算。然后计算一千赫兹的增益电平，并从此计算运算放大器的单位增益频率。计算用于所述运算放大器的补偿电容器的值，然后计算运算放大器的第一级的跨导。然后确定运算放大器的第一级的总直流增益电平和输出电阻。第一级和第二级的跨导，第一级的输出电阻与负载电容和电阻将用于合成运算放大器的晶体管尺寸和偏置电流电平。然后对该设计进行模拟以获得稳定性，并且重复该方法直到达到稳定性。

9. 发明授权

US6043680A 5V tolerant I/O buffer 失效
标题翻译： 5V耐受I / O缓冲器
公开(公告)号：US6043680A
公开(公告)日：2000-03-28
申请号：US17134
申请日：1998-02-02
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03K19/003 , H03K17/16 , H03K19/0185
CPC分类号： H03K19/00315
摘要： A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transistor in series with the existing p-channel transistor. The extra p-channel transistor and its parasitic diode are wired so that they will not conduct, i.e. the extra transistor is off and the parasitic diode is back-biased, when a 5 volt input signal is applied to the output of the tristate input/output buffer. Two additional transistors are used to control the on/off state of the extra p-channel transistor.
摘要翻译：公开了一种电路和方法，以提供三输入/输出缓冲器，其与使用3伏特电源工作的施加到其输出节点的5伏输入信号兼容。这是通过插入与现有p沟道晶体管串联的额外的p沟道晶体管来实现的。额外的p沟道晶体管及其寄生二极管被布线，使得它们不会导通，即，当5V输入信号施加到三态输入/输出的输出端时，额外的晶体管关闭，寄生二极管反向偏置，输出缓冲区。使用两个额外的晶体管来控制额外的p沟道晶体管的导通/截止状态。

10. 发明授权

US06031401A Clock waveform synthesizer 失效
标题翻译：时钟波形合成器
公开(公告)号：US06031401A
公开(公告)日：2000-02-29
申请号：US92581
申请日：1998-06-08
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： G06F1/025 , G06F1/08 , H03K5/00 , H03K5/156 , H03K3/017
CPC分类号： H03K5/156 , G06F1/025 , G06F1/08 , H03K5/00006
摘要： A clock waveform synthesizer that will create a timing signal that is a multiple of the frequency of an master clock is disclosed and has the capability to programmably adjust the rising edges and falling edges of the synthesized waveform within the period of the master clocks. The clock waveform synthesizer has a multi-tapped delay line. The multi-tapped delay line will create replications of the master clock that are incrementally delayed from the master clock to create a plurality of delay signals. A fraction of the plurality of delay signals will be the inputs to each of a plurality of multiplexers. A select port on each of the multiplexers will receive a select signal to choose one delay signal of the fraction of the plurality of delay signals. The one selected delay signals will be the input to the set terminals and reset terminals of a plurality of edge-triggered set/reset flip-flops. The edge-triggered set/reset flip-flop has an output terminal which will transit from a first logic level to a second logic level when the one selected delay signals is received at the set terminal and will transit from the second logic level to the first logic level when the one selected delay signal is received at the reset terminal. The outputs of the plurality of edge-triggered set/reset flip-flops are connected to the inputs of a combining logic gate, which will combine the signals at the outputs of the edge-triggered set/reset flip-flops to form the synthesized timing signal.
摘要翻译：公开了一种时钟波形合成器，其将产生作为主时钟频率的倍数的定时信号，并且具有在主时钟周期内可编程地调整合成波形的上升沿和下降沿的能力。时钟波形合成器具有多抽头延迟线。多抽头延迟线将产生从主时钟递增延迟的主时钟的复制以产生多个延迟信号。多个延迟信号中的一部分将是多个多路复用器中的每一个的输入。每个复用器上的选择端口将接收选择信号以选择多个延迟信号的一部分的一个延迟信号。一个选择的延迟信号将是多个边沿触发的设置/复位触发器的设置端子和复位端子的输入。边沿触发的设置/复位触发器具有输出端子，当在所设置的端子处接收到一个所选择的延迟信号并且将从第二逻辑电平转移到第一逻辑电平时，该输出端将从第一逻辑电平转换到第二逻辑电平在复位端接收一个所选择的延迟信号时的逻辑电平。多个边沿触发的设置/复位触发器的输出连接到组合逻辑门的输入端，组合逻辑门将组合边沿触发的设置/复位触发器的输出处的信号以形成合成时序信号。

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