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21. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

22. 发明申请

US20100254209A1 Ultra-Low Leakage Memory Architecture 有权
标题翻译：超低泄漏内存架构
公开(公告)号：US20100254209A1
公开(公告)日：2010-10-07
申请号：US12694032
申请日：2010-01-26
申请人： Cheng Hung Lee , Hung-Jen Liao
发明人： Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/063
摘要： An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.
摘要翻译：集成电路结构包括有源电源线和数据保持电源线。存储器宏连接到有源电源线和数据保持电源线。存储器宏包括存储单元阵列和开关。该开关被配置为在将存储单元阵列连接到有源电源线之间切换连接，并将存储单元阵列连接到数据保持电源线。数据保持电源线在存储器宏之外。

23. 发明授权

US07701755B2 Memory having improved power design 有权
标题翻译：内存具有改进的电源设计
公开(公告)号：US07701755B2
公开(公告)日：2010-04-20
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

24. 发明申请

US20080258813A1 Sense Amplifiers Operated Under Hamming Distance Methodology 有权
标题翻译：在汉明距离方法下运行的感应放大器
公开(公告)号：US20080258813A1
公开(公告)日：2008-10-23
申请号：US11737093
申请日：2007-04-18
申请人： Chia-Wei Wang , Hong-Chen Cheng , Lee Cheng Hung , Hung-Jen Liao
发明人： Chia-Wei Wang , Hong-Chen Cheng , Lee Cheng Hung , Hung-Jen Liao
IPC分类号： H03F3/45
CPC分类号： G11C7/065
摘要： A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs.
摘要翻译：半导体器件包括耦合到输入端的第一读出放大器，用于产生第一输出; 第二读出放大器耦合到输入以产生第二输出; 以及耦合到所述输入的第三读出放大器，用于产生第三输出，其中基于所述第一，第二和第三输出的逻辑状态的组合产生放大所述输入的第四输出。

25. 发明申请

US20080229161A1 MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF 审中-公开
标题翻译：记忆产品及其制造方法
公开(公告)号：US20080229161A1
公开(公告)日：2008-09-18
申请号：US11686996
申请日：2007-03-16
申请人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/70 , G11C29/80 , G11C2029/5004 , H01L22/22 , H01L27/1052
摘要： Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.
摘要翻译：内存产品及其制造方法。存储器产品包括至少一个存储器单元和至少一个冗余存储单元。存储单元和冗余存储单元具有不同的物理或电子特性。如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

26. 发明申请

US20070253239A1 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US20070253239A1
公开(公告)日：2007-11-01
申请号：US11582116
申请日：2006-10-17
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an α ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a β ratio of between about 1.45 and 5.
摘要翻译：读优选SRAM单元包括具有第一驱动电流的上拉MOS器件，耦合到上拉MOS器件的下拉MOS器件，具有第二驱动电流的下拉MOS器件，栅极MOS器件具有耦合到上拉MOS器件和下拉MOS器件的第三驱动电流。第一驱动电流和第三驱动电流优选地具有在约0.5和约1之间的α比率。第二驱动电流和第三驱动电流优选具有在约1.45和5之间的β比率。

27. 发明申请

US20070247950A1 Memory device with reduced stand-by mode power consumption 审中-公开
标题翻译：具有降低备用模式功耗的存储器件
公开(公告)号：US20070247950A1
公开(公告)日：2007-10-25
申请号：US11407593
申请日：2006-04-20
申请人： Cheng Lee , Hung-Jen Liao
发明人： Cheng Lee , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C8/10
摘要： The present invention discloses a memory device. In one embodiment of the present invention, the memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines. At least one word line decoder is coupled to the word lines for selecting the memory cell for read or write operation. The word line decoder includes at least one last stage driver having at least one PMOS transistor and at least one NMOS transistor, the PMOS transistor having a threshold voltage substantially higher than that of the NMOS transistor, thereby reducing the power consumption of the memory device in the stand-by mode.
摘要翻译：本发明公开了一种存储装置。在本发明的一个实施例中，存储器件包括至少一个存储器阵列，其具有由多个字线和位线寻址的多个存储器单元。至少一个字线解码器耦合到字线，用于选择用于读或写操作的存储单元。字线解码器包括至少一个具有至少一个PMOS晶体管和至少一个NMOS晶体管的最后一级驱动器，PMOS晶体管具有基本上高于NMOS晶体管的阈值电压的阈值电压，从而降低了存储器件的功耗备用模式。

28. 发明申请

US20070242555A1 WORD-LINE DRIVER FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的字线驱动器
公开(公告)号：US20070242555A1
公开(公告)日：2007-10-18
申请号：US11406984
申请日：2006-04-18
申请人： Cheng Lee , Hung-Jen Liao
发明人： Cheng Lee , Hung-Jen Liao
IPC分类号： G11C8/00 , G11C5/14
CPC分类号： G11C8/08
摘要： A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designating an output of the first inverter and an input of the second inverter, the first inverter having a NMOS transistor with a controllable first source, and a first pull-up circuitry coupled between a positive supply voltage and the first node and selectively activated by a first control signal, wherein when the first source is set to the positive supply voltage and the first control signal is set to a complementary supply voltage of the positive supply voltage, the first node is pulled up to the positive supply voltage to ensure an output of the second inverter is pulled down to the complementary supply voltage.
摘要翻译：字线驱动器具有来自字线解码器的输入和用于驱动字线的输出。字线驱动器包括串联连接在输入和输出之间的多个反相器，包括具有指定第一反相器的输出的第一节点和第二反相器的输入的第一和第二反相器，第一反相器具有NMOS 具有可控第一源的晶体管，以及耦合在正电源电压和第一节点之间并由第一控制信号选择性地激活的第一上拉电路，其中当第一源被设置为正电源电压和第一控制信号设定为正电源电压的互补电源电压，将第一节点上拉至正电源电压，以确保将第二逆变器的输出下拉至互补电源电压。

29. 发明申请

US20070206401A1 Electrical fuse device with dummy cells for ESD protection 有权
标题翻译：具有用于ESD保护的虚设电池的电熔丝装置
公开(公告)号：US20070206401A1
公开(公告)日：2007-09-06
申请号：US11368213
申请日：2006-03-02
申请人： Sung-Chieh Lin , Hung-Jen Liao
发明人： Sung-Chieh Lin , Hung-Jen Liao
IPC分类号： G11C5/14 , G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse device includes at least one electrical fuse cell having a first switch device serially coupled with an electrical fuse representing a logic value; and at least one dummy cell having a second switch device coupled to the first switch device via a common word line, the second switch device having a trigger-on voltage lower than that of the first device, such that the second switch becomes conductive earlier than the first switch device for bypassing an electrostatic discharge (ESD) current therethrough during an ESD event.
摘要翻译：电熔丝装置包括至少一个电熔丝单元，其具有与表示逻辑值的电熔丝串联耦接的第一开关装置; 以及至少一个具有通过公共字线耦合到第一开关装置的第二开关装置的虚拟电池，所述第二开关装置的触发电压低于第一装置的触发电压，使得第二开关比用于在ESD事件期间绕过静电放电（ESD）电流通过的第一开关装置。

30. 发明申请

US20070159231A1 Multi-state electrical fuse 有权
公开(公告)号：US20070159231A1
公开(公告)日：2007-07-12
申请号：US11328780
申请日：2006-01-10
申请人： Yung-Lung Lin , Jui-Jen Wu , Hung-Jen Liao
发明人： Yung-Lung Lin , Jui-Jen Wu , Hung-Jen Liao
IPC分类号： H01H37/76
CPC分类号： G11C11/56 , G11C17/18
摘要： An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

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