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1. 发明申请

US20080229161A1 MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF 审中-公开
标题翻译：记忆产品及其制造方法
公开(公告)号：US20080229161A1
公开(公告)日：2008-09-18
申请号：US11686996
申请日：2007-03-16
申请人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/70 , G11C29/80 , G11C2029/5004 , H01L22/22 , H01L27/1052
摘要： Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.
摘要翻译：内存产品及其制造方法。存储器产品包括至少一个存储器单元和至少一个冗余存储单元。存储单元和冗余存储单元具有不同的物理或电子特性。如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

2. 发明授权

US07613054B2 SRAM device with enhanced read/write operations 有权
标题翻译：具有增强的读/写操作的SRAM器件
公开(公告)号：US07613054B2
公开(公告)日：2009-11-03
申请号：US11924437
申请日：2007-10-25
申请人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.
摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

3. 发明授权

US07952911B2 SRAM cell array structure 有权
标题翻译： SRAM单元阵列结构
公开(公告)号：US07952911B2
公开(公告)日：2011-05-31
申请号：US12111905
申请日：2008-04-29
申请人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/419
摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

4. 发明申请

US20090109768A1 SRAM Device with Enhanced Read/Write Operations 有权
标题翻译：具有增强读/写操作的SRAM器件
公开(公告)号：US20090109768A1
公开(公告)日：2009-04-30
申请号：US11924437
申请日：2007-10-25
申请人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.
摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

5. 发明申请

US20060256635A1 Memory system with bit-line discharging mechanism 有权
标题翻译：具有位线放电机制的存储器系统
公开(公告)号：US20060256635A1
公开(公告)日：2006-11-16
申请号：US11128846
申请日：2005-05-13
申请人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C17/12 , G11C7/12 , G11C17/18
摘要： A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.
摘要翻译：公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线，在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。

6. 发明授权

US07190626B2 Memory system with bit-line discharging mechanism 有权
标题翻译：具有位线放电机制的存储器系统
公开(公告)号：US07190626B2
公开(公告)日：2007-03-13
申请号：US11128846
申请日：2005-05-13
申请人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C17/12 , G11C7/12 , G11C17/18
摘要： A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.
摘要翻译：公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线，在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。

7. 发明授权

US08675439B2 Bit line voltage bias for low power memory design 有权
标题翻译：用于低功耗存储器设计的位线电压偏置
公开(公告)号：US08675439B2
公开(公告)日：2014-03-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

8. 发明申请

US20130094307A1 BIT LINE VOLTAGE BIAS FOR LOW POWER MEMORY DESIGN 有权
标题翻译：用于低功率存储器设计的位线电压偏置
公开(公告)号：US20130094307A1
公开(公告)日：2013-04-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen CHENG , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen CHENG , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

9. 发明授权

US07913215B2 Memory macro with irregular edge cells 有权
标题翻译：具有不规则边缘单元格的内存宏
公开(公告)号：US07913215B2
公开(公告)日：2011-03-22
申请号：US11493405
申请日：2006-07-26
申请人： Chung-Cheng Chou , Cheng-Hung Lee
发明人： Chung-Cheng Chou , Cheng-Hung Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.
摘要翻译：存储器宏包括设置在存储器阵列的第一区域中的第一组单元，以及设置在第一区域的边缘处的与物理尺寸的第一组单元不同的第二组单元，用于改善第一区域的鲁棒性存储器阵列边缘的单元格。

10. 发明申请

US20080028351A1 Memory macro with irregular edge cells 有权
标题翻译：具有不规则边缘单元格的内存宏
公开(公告)号：US20080028351A1
公开(公告)日：2008-01-31
申请号：US11493405
申请日：2006-07-26
申请人： Chung-Cheng Chou , Cheng-Hung Lee
发明人： Chung-Cheng Chou , Cheng-Hung Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.
摘要翻译：存储器宏包括设置在存储器阵列的第一区域中的第一组单元，以及设置在第一区域的边缘处的与物理尺寸的第一组单元不同的第二组单元，用于改善第一区域的鲁棒性存储器阵列边缘的单元格。

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