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    • 21. 发明授权
    • Semiconductor ceramic composition and process for producing the same
    • 半导体陶瓷组合物及其制造方法
    • US07993547B2
    • 2011-08-09
    • US12444895
    • 2007-10-26
    • Takeshi ShimadaKazuya Toji
    • Takeshi ShimadaKazuya Toji
    • H01B1/08C04B35/46
    • H01C7/025C04B35/4682C04B35/62675C04B35/62685C04B2235/3201C04B2235/3208C04B2235/3234C04B2235/3251C04B2235/3294C04B2235/3298C04B2235/3418C04B2235/5436C04B2235/6562C04B2235/6565C04B2235/6584H01C17/06533
    • It is intended to provide a semiconductor ceramic composition in which a part of Ba in BaTiO3 is substituted with Bi—Na, which is capable of restraining the evaporation of Bi in the calcination step, is capable of restraining the compositional deviation of Bi—Na thereby suppressing the formation of different phases, is capable of further reducing the resistivity at room temperature, and is capable of restraining the fluctuation of the Curie temperature; and to provide a production process of the same. When a calcined Ba(TiM)O3 powder (M is a semiconductor dopant) and a calcined (BiNa)TiO3 powder are separately prepared and the Ba(TiM)O3 powder is calcined at a relatively high temperature while the (BiNa)TiO3 powder is at a relatively low temperature, both at the most suitable temperatures for them, then the evaporation of Bi may be retarded and the compositional deviation of Bi—Na may be thereby suppressed to inhibit the formation of different phases; and when these calcined powders are mixed, formed and sintered, then a semiconductor ceramic composition which has a low resistivity at room temperature and is capable of restraining the fluctuation of the Curie temperature can be obtained.
    • 旨在提供一种半导体陶瓷组合物,其中BaTiO 3中的Ba的一部分被Bi-Na代替,Bi-Na能够抑制在煅烧步骤中Bi的蒸发,因此能够抑制Bi-Na的组成偏差 抑制不同相的形成,能够进一步降低室温下的电阻率,并且能够抑制居里温度的波动; 并提供相同的生产工艺。 当分别制备煅烧的Ba(TiM)O 3粉末(M是半导体掺杂剂)和煅烧(BiNa)TiO 3粉末时,并且在(BiNa)TiO 3粉末是相对较高的温度下煅烧Ba(TiM)O 3粉末, 在相对较低的温度下,在它们最适合的温度下,则Bi的蒸发可能被延迟,并且可以抑制Bi-Na的组成偏差以抑制不同相的形成; 并且当将这些煅烧粉末混合,形成和烧结时,​​可以获得在室温下具有低电阻率并且能够抑制居里温度波动的半导体陶瓷组合物。
    • 30. 发明授权
    • Multi-processor system
    • 多处理器系统
    • US07320056B2
    • 2008-01-15
    • US11285184
    • 2005-11-23
    • Takeshi ShimadaTatsuru NakagakiAkihiro Kobayashi
    • Takeshi ShimadaTatsuru NakagakiAkihiro Kobayashi
    • G06F13/16
    • G06F12/0831G06F12/0813G06F13/1663
    • Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When a processor performs writing to a shared memory space, the processor notifies an update notification bus corresponding to the conventional global bus, to which address the update is to be performed. The other processors which have detected this notification inhibit access to that address and wait for the write data to be sent to the address via the dedicated line. When the data has arrived, the data is written into the corresponding address. Here, the data is also written into the corresponding address, thereby maintaining the cache coherency. Moreover, when transmitting a write address, it is necessary to acquire the bus use right while data transmission is performed by using the dedicated line, which significantly reduces the time required for acquiring the bus use right.
    • 通过设置在每个处理器和共享存储器之间的高速专用线来执行用于将数据写入共享存储器的数据传输。 当处理器对共享存储器空间进行写入时,处理器通知对应于常规全局总线的更新通知总线,该更新将被执行到该地址。 检测到该通知的其他处理器禁止访问该地址,并等待通过专用线将写入数据发送到地址。 数据到达时,数据写入相应的地址。 这里,数据也被写入相应的地址,从而保持高速缓存一致性。 此外,当发送写入地址时,需要通过使用专用线来执行数据传输时获取总线使用权,这大大减少了获取总线使用权所需的时间。