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21. 发明授权

US06235642B1 Method for reducing plasma charging damages 有权
标题翻译：减少等离子体充电损害的方法
公开(公告)号：US06235642B1
公开(公告)日：2001-05-22
申请号：US09483580
申请日：2000-01-14
申请人： Tzung-Han Lee , Mu-Chun Wang
发明人： Tzung-Han Lee , Mu-Chun Wang
IPC分类号： H01L2100
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing plasma charging damages is disclosed. The method includes the following steps: define cell regions and scribe line regions on a substrate. Then, form a trench region on one of the scribe line regions wherein the bottom part of the trench region is in contact with the substrate. Thereupon fill the trench region with polysilicon substances. After the filling, deposit a pad polysilicon layer on the trench region. Following the pad layer formation, construct an integrated circuit as routine practice. During the circuit fabrication, several channel regions are formed in connection with the pad layer. Next, fabricate various conductive structures on the scribe line regions and link them also to the channel regions. Any excess charge in the scribe line region would be collected by the conductive structures and directed by the channel region to the trench region for grounding. Upon completion of the device fabrication, insulate the process to prevent charges from shifting back to the scribe line regions and damaging the device.
摘要翻译：公开了一种减少等离子体充电损伤的方法。该方法包括以下步骤：在衬底上限定单元区域和划线区域。然后，在其中沟槽区域的底部与衬底接触的划线区域之一上形成沟槽区域。于是填补了多晶硅物质的沟槽区域。在填充之后，在沟槽区域上沉积焊盘多晶硅层。在衬垫层形成之后，构建集成电路作为常规实践。在电路制造期间，与衬垫层相连接地形成几个通道区域。接下来，在划线区域上制造各种导电结构并将它们连接到沟道区。划线区域中的任何多余的电荷将被导电结构收集并被沟道区域引导到沟槽区域进行接地。在器件制造完成后，绝缘过程以防止电荷转回划线区域并损坏器件。

22. 发明授权

US06229347B1 Circuit for evaluating an asysmetric antenna effect 有权
标题翻译：评估非对称天线效应的电路
公开(公告)号：US06229347B1
公开(公告)日：2001-05-08
申请号：US09228366
申请日：1999-01-11
申请人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
发明人： Mu-Chun Wang , Chau-Neng Wu , Shiang Huang-Lu
IPC分类号： H03K522
CPC分类号： H03F3/45183 , H03F2203/45674 , H03K5/2418 , H03K5/2481
摘要： A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.
摘要翻译：提供了一种用于评估晶体管对的不对称天线效应的电路，其可以通过使用双极或互补金属氧化物半导体（CMOS）晶体管来实现差分放大器来实现，其中具有相似特性的一对晶体管Q1和Q2具有连接的。晶体管Q1和Q2具有例如一个多晶硅层和三个金属层的结构，其中第二金属层M2和第三金属层M3用于信号输入，并且金属层M1靠近栅极氧化物层使用晶体管Q1和Q2两者来获得差分天线比。差分放大器包括用作有源负载的晶体管Q3和Q4以及用于调整电压增益的晶体管Q5。

23. 发明授权

US6110841A Method for avoiding plasma damage 有权
标题翻译：避免血浆损伤的方法
公开(公告)号：US6110841A
公开(公告)日：2000-08-29
申请号：US418144
申请日：1999-10-14
申请人： Mu-Chun Wang , Yih-Jau Chang
发明人： Mu-Chun Wang , Yih-Jau Chang
IPC分类号： H01L21/265 , H01L21/31
CPC分类号： H01L21/26513
摘要： A method for avoiding plasma damage. In a semiconductor substrate of a first conductive type, a second conductive type well is formed. While forming the second conductive well, a high-energy dopant is doped into the semiconductor substrate. The high energy makes a depletion region between the substrate and the well have defects. A leakage path is thus formed. The leakage path can direct any charged carriers coming from plasma to avoid accumulation of the charged carriers in the well. Thus, the electrical characteristics of the well or even the quality of gate oxide formed thereon is prevented from being degraded.
摘要翻译：一种避免血浆损伤的方法。在第一导电类型的半导体衬底中形成第二导电型阱。在形成第二导电阱的同时，将高能掺杂剂掺杂到半导体衬底中。高能量使得衬底和阱之间的耗尽区具有缺陷。从而形成泄漏路径。泄漏路径可以引导来自等离子体的任何带电荷的载流子以避免带电载流子在阱中的积聚。因此，防止形成在其上的阱氧化物的阱的电特性或甚至质量劣化。

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