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1. 发明授权

US08063444B2 Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability in integrated circuit 有权
标题翻译：在集成电路中具有静电放电（ESD）保护能力的横向扩散金属氧化物半导体（LDMOS）器件
公开(公告)号：US08063444B2
公开(公告)日：2011-11-22
申请号：US12426151
申请日：2009-04-17
申请人： Yih-Jau Chang
发明人： Yih-Jau Chang
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L27/0248 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/7835
摘要： Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+ doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+ doped source region and a P+ diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+ doped source region and the N+ doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer. The punch-through voltage or the breakdown voltage of the interface can be adapted by regulating the P+ or N+ dosage to exceed the breakdown voltage of the LDNMOS transistor or the LDPMOS transistor. It can be able to effectively reduce the breakdown voltage or the punch-through voltage relative to the semiconductor substrate under the drain region, thus increasing ESD protection.
摘要翻译：针对集成电路提出了具有静电放电（ESD）保护能力的横向扩散金属氧化物半导体（LDMOS）器件。 LDMOS器件包括其上具有外延层的半导体衬底。图案化隔离设置在外延层上，由此限定第一有源区和第二有源区。在第一有源区中形成N型双扩散漏极（NDDD）区域，并且在NDDD区域中设置N +掺杂漏极区域。在第二有源区域中形成P体扩散区域，其中NDDD区域和P体扩散区域以暴露外延层的预定距离分离。在P体扩散区域中设置N +掺杂源极区域和P +扩散区域。栅极结构设置在N +掺杂源极区域和N +掺杂漏极区域之间。在半导体和外延层之间形成附加的重掺杂区域。可以通过调节P +或N +剂量来超过LDNMOS晶体管或LDPMOS晶体管的击穿电压来适应接触的穿通电压或击穿电压。能够有效地降低漏极区域下的相对于半导体衬底的击穿电压或穿通电压，从而增加ESD保护。

2. 发明申请

US20100148256A1 LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CAPABILITY IN INTEGRATED CIRCUIT 有权
标题翻译：具有静电放电（ESD）保护能力的集成电路的侧向扩散金属氧化物半导体（LDMOS）器件
公开(公告)号：US20100148256A1
公开(公告)日：2010-06-17
申请号：US12426151
申请日：2009-04-17
申请人： Yih-Jau Chang
发明人： Yih-Jau Chang
IPC分类号： H01L29/78 , H01L23/62
CPC分类号： H01L29/7816 , H01L27/0248 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/7835
摘要： Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+ doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+ doped source region and a P+ diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+ doped source region and the N+ doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer. The punch-through voltage or the breakdown voltage of the interface can be adapted by regulating the P+ or N+ dosage to exceed the breakdown voltage of the LDNMOS transistor or the LDPMOS transistor. It can be able to effectively reduce the breakdown voltage or the punch-through voltage relative to the semiconductor substrate under the drain region, thus increasing ESD protection.
摘要翻译：针对集成电路提出了具有静电放电（ESD）保护能力的横向扩散金属氧化物半导体（LDMOS）器件。 LDMOS器件包括其上具有外延层的半导体衬底。图案化隔离设置在外延层上，从而限定第一有源区和第二有源区。在第一有源区中形成N型双扩散漏极（NDDD）区域，并且在NDDD区域中设置N +掺杂漏极区域。在第二有源区域中形成P体扩散区域，其中NDDD区域和P体扩散区域以暴露外延层的预定距离分离。在P体扩散区域中设置N +掺杂源极区域和P +扩散区域。栅极结构设置在N +掺杂源极区域和N +掺杂漏极区域之间。在半导体和外延层之间形成附加的重掺杂区域。可以通过调节P +或N +剂量来超过LDNMOS晶体管或LDPMOS晶体管的击穿电压来适应接触的穿通电压或击穿电压。能够有效地降低漏极区域下的相对于半导体衬底的击穿电压或穿通电压，从而增加ESD保护。

3. 发明授权

US6114226A Method of manufacturing electrostatic discharge protective circuit 有权
标题翻译：制造静电放电保护电路的方法
公开(公告)号：US6114226A
公开(公告)日：2000-09-05
申请号：US246608
申请日：1999-02-08
申请人： Yih-Jau Chang , Chen-Chung Hsu
发明人： Yih-Jau Chang , Chen-Chung Hsu
IPC分类号： H01L21/8234 , H01L27/02 , H01L21/04
CPC分类号： H01L27/027 , H01L21/823443 , H01L21/823468 , H01L27/0255
摘要： A method for manufacturing an electrostatic discharge (ESD) protective circuit. By using the method according to the invention, since the Zener diode, which has low trigger voltage and low power consumption, is formed in the electrostatic protective circuit, the protective ability of the ESD protective circuit is greatly improved as the integration is relatively high. Furthermore, it is necessary to use an extra photo mask as the ESD implantation step and the Zener breakdown implantation step are performed when the internal circuit and the ESD protective circuit are formed simultaneously, so that the cost is reduced.
摘要翻译：一种制造静电放电（ESD）保护电路的方法。通过使用本发明的方法，由于在静电保护电路中形成具有低触发电压和低功耗的齐纳二极管，因此集成度相对较高，ESD保护电路的保护能力大大提高。此外，需要使用额外的光掩模作为ESD注入步骤，并且当内部电路和ESD保护电路同时形成时进行齐纳击穿注入步骤，从而降低成本。

4. 发明授权

US5723373A Method of making porous-Si capacitors for high density drams cell 失效
标题翻译：制造用于高密度电池的多孔硅电容器的方法
公开(公告)号：US5723373A
公开(公告)日：1998-03-03
申请号：US746857
申请日：1996-11-18
申请人： Yih-Jau Chang , Shye-Lin Wu
发明人： Yih-Jau Chang , Shye-Lin Wu
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/82 , H01L28/84
摘要： The present invention is a method of manufacturing porous-Si capacitors for use in semiconductor memories. The present invention uses a silicon oxide layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the polysilicon layer and to etch away the remaining HSG-Si. Next, an oxide layer which is in micro grooves is removed to define a porous-Si bottom storage. The present invention can be used to increase the surface area of the capacitor.
摘要翻译：本发明是制造用于半导体存储器的多孔硅电容器的方法。本发明使用氧化硅层作为蚀刻掩模来蚀刻多晶硅层以形成多孔Si结构。执行蚀刻工艺以蚀刻多晶硅层的一部分并蚀刻掉剩余的HSG-Si。接下来，去除微槽中的氧化物层以限定多孔Si底部储存。本发明可以用于增加电容器的表面积。

5. 发明授权

US4478679A Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors 失效
标题翻译：用于在MOS半导体的源极和漏极区域上放置阻挡金属的自对准工艺
公开(公告)号：US4478679A
公开(公告)日：1984-10-23
申请号：US556722
申请日：1983-11-30
申请人： Jenq-Sian Chang , Yih-Jau Chang
发明人： Jenq-Sian Chang , Yih-Jau Chang
IPC分类号： H01L21/336 , H01L21/768 , H01L29/417 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L29/66575 , H01L21/7684 , H01L21/76895 , H01L29/41775 , H01L29/41783
摘要： A self-aligning process for adding a barrier metal to the source and drain regions of metal oxide semiconductors is presented. An oxide sidewall spacer is first formed on the sides of upwardly protruding gate regions. A barrier metal is then added to the entire surface, followed by adding a layer of resist material. The resist material is added in layers with each layer spun until the top surface is nearly smooth. An anisotropical etch is done to remove the resist everywhere except over the source and drain regions, which regions are depressed due to the upwardly protruding gate region and a surrounding upwardly protruding insulating material. The exposed barrier metal is etched away and the remaining resist is stripped, leaving a layer of barrier metal only over the source and drain regions.
摘要翻译：提出了一种用于向金属氧化物半导体的源极和漏极区域添加阻挡金属的自对准工艺。首先在向上突出的栅极区域的侧面上形成氧化物侧壁间隔物。然后将阻挡金属加入整个表面，然后加入一层抗蚀剂材料。将抗蚀剂材料分层加入，每层纺丝直到顶表面几乎平滑。进行各向异性蚀刻以去除除源极和漏极区域之外的所有其它抗蚀剂，该区域由于向上突出的栅极区域和周围的向上突出的绝缘材料而被压下。将暴露的阻挡金属蚀刻掉，剩余的抗蚀剂被剥离，仅在源极和漏极区域上留下一层阻挡金属。

6. 发明授权

US06255809B1 Method for measuring capacitance of passive device region 有权
标题翻译：无源器件区域电容测量方法
公开(公告)号：US06255809B1
公开(公告)日：2001-07-03
申请号：US09327895
申请日：1999-06-08
申请人： Sheng-Hsing Yang , Yih-Jau Chang
发明人： Sheng-Hsing Yang , Yih-Jau Chang
IPC分类号： G01R2726
CPC分类号： G01R27/2605 , H01L22/14
摘要： A method for measuring a capacitance of a passive device region. The passive device region is formed on a substrate having a conductive type different from that of the passive device region. Two bias voltages are applied to two terminals of the passive device region. By measuring the distance between these two terminals and the width of the passive device region, plus the grading coefficients of both area effect and sidewall effect, capacitance induced at both terminals can be derived.
摘要翻译：一种用于测量无源器件区域的电容的方法。无源器件区域形成在具有不同于无源器件区域的导电类型的衬底上。两个偏置电压施加到无源器件区域的两个端子。通过测量这两个端子之间的距离和无源器件区域的宽度，加上面积效应和侧壁效应的分级系数，可以推导出两端引起的电容。

7. 发明授权

US08252652B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08252652B2
公开(公告)日：2012-08-28
申请号：US12748703
申请日：2010-03-29
申请人： Yih-Jau Chang , Shang-Hui Tu , Gene Sheu , Yi-Fong Chang , Nithin Devarajulu Palavalli
发明人： Yih-Jau Chang , Shang-Hui Tu , Gene Sheu , Yi-Fong Chang , Nithin Devarajulu Palavalli
IPC分类号： H01L21/336 , H01L29/06
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659
摘要： A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.
摘要翻译：提供半导体结构。在第一导电型基板上形成第二导电类型阱区。在第一导电型基板上形成第二导电型扩散源极和第二导电型扩散漏极。在第二导电型扩散源和第二导电型扩散漏极之间的第二导电类型阱区上形成栅极结构。第一导电型掩埋环沿水平方向布置，并形成在第二导电类型阱区中，并将第二导电类型阱区划分为上漂移区和下漂移区。

8. 发明授权

US06319850B1 Method of forming dielectric layer with low dielectric constant 失效
标题翻译：形成低介电常数介电层的方法
公开(公告)号：US06319850B1
公开(公告)日：2001-11-20
申请号：US09294541
申请日：1999-04-19
申请人： Yih-Jau Chang , Chen-Chung Hsu
发明人： Yih-Jau Chang , Chen-Chung Hsu
IPC分类号： H01L2131
CPC分类号： H01L21/02131 , H01L21/02203 , H01L21/02304 , H01L21/02321 , H01L21/02337 , H01L21/02351 , H01L21/02362 , H01L21/31695
摘要： A method for forming a dielectric layer with a low dielectric constant (low-k) is described. A semiconductor substrate is provided. A dielectric layer is formed on the substrate. A doping step is performed on the dielectric layer. An annealing step is performed and a gas is simultaneously fed so that the dielectric layer is converted into the low-k dielectric layer.
摘要翻译：描述了形成具有低介电常数（低-k）的电介质层的方法。提供半导体衬底。在基板上形成电介质层。在电介质层上进行掺杂步骤。进行退火步骤，同时进料气体，使得电介质层转化为低k电介质层。

9. 发明授权

US6150261A Method of fabricating semiconductor device for preventing antenna effect 有权
标题翻译：制造防止天线效应的半导体器件的方法
公开(公告)号：US6150261A
公开(公告)日：2000-11-21
申请号：US318235
申请日：1999-05-25
申请人： Chen-Chung Hsu , Yih-Jau Chang
发明人： Chen-Chung Hsu , Yih-Jau Chang
IPC分类号： H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L24/02 , H01L21/76892 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/13091
摘要： A method of fabricating a semiconductor device for preventing an antenna effect. In the invention, there is no additional mask layer or specific process performed. Thus, the fabrication cost does not increase. In addition, extra electrons are released through a path formed in the invention during the plasma-etching step. An antenna effect thus does not occur. The reliability of the semiconductor device is increased.
摘要翻译：一种制造用于防止天线效应的半导体器件的方法。在本发明中，没有附加的掩模层或特定的处理。因此，制造成本不增加。此外，在等离子蚀刻步骤期间，通过本发明中形成的路径释放额外的电子。因此不会发生天线效应。半导体器件的可靠性提高。

10. 发明授权

US5670397A Dual poly-gate deep submicron CMOS with buried contact technology 失效
标题翻译：双层多晶硅深亚微米CMOS埋层接触技术
公开(公告)号：US5670397A
公开(公告)日：1997-09-23
申请号：US783754
申请日：1997-01-16
申请人： Yih-Jau Chang , Shye-Lin Wu
发明人： Yih-Jau Chang , Shye-Lin Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET. A PMOS LDD with halo doping profile is implanted. A second LPD oxide is selectively formed in the second trenches. A second heavy ion implantation is performed into the polysilicon stack layer to form the source, drain, gate and buried contacts of the PMOSFET. A thermal treatment is used to condense the LPD oxide and to activate the S/D implants and diffuse the heavy implants from the polysilicon stack layer into the substrate to form the buried contacts.
摘要翻译：具有埋入触点的CMOS器件使用多晶硅堆叠层和双阱和液相沉积（LPD）工艺形成。在基板上形成栅极氧化层和第一多晶硅层。然后蚀刻栅极氧化物和第一多晶硅层以形成栅极结构。在栅极结构上形成多晶硅堆叠层。多晶硅堆叠层和第一多晶硅层被各向异性地干蚀刻，形成第一沟槽，其暴露出栅极氧化物的部分和限定用于NMOSFET的S / D区域的衬底的部分。注入具有晕圈掺杂分布的NMOS轻掺杂漏极（LDD）。在第一沟槽中选择性地形成第一LPD氧化物。随后，对多晶硅叠层进行第一次重离子注入，以形成NMOSFET的源极，漏极，栅极和埋入触点。沟槽形成在多晶硅堆叠层和第一多晶硅层中以限定用于PMOSFET的S / D区域和埋入触点。植入具有晕圈掺杂分布的PMOS LDD。在第二沟槽中选择性地形成第二LPD氧化物。对多晶硅堆叠层进行第二次重离子注入以形成PMOSFET的源极，漏极，栅极和埋入触点。热处理用于冷凝LPD氧化物并激活S / D植入物，并将重掺杂物从多晶硅堆叠层扩散到衬底中以形成掩埋触点。

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