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21. 发明授权

US06319831B1 Gap filling by two-step plating 有权
标题翻译：间隙填充通过两步电镀
公开(公告)号：US06319831B1
公开(公告)日：2001-11-20
申请号：US09507904
申请日：2000-02-22
申请人： Wen-Jye Tsai , Ming-Hsing Tsai
发明人： Wen-Jye Tsai , Ming-Hsing Tsai
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/76877
摘要： A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by depositing the copper in two stages with an optional dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brighteners and levelers. A first copper layer is plated at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio openings are covered with a substantial thickness of a uniform, high quality copper coating. During plating, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. Optionally, the brightener is replenished in these regions during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the openings are filled and additional copper is deposited over them at a high deposition rate. A benefit of the high current density deposition is that depletion of leveler chemical in the openings enhances the growth rate of copper at the base of the openings thereby favoring growth from bottom up. This avoids the formation of voids in the openings. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.
摘要翻译：描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。该方法设计为通过在两个阶段之间以可选的停留时间两段沉积铜来提供良好的覆盖和间隙填充能力以及高的生产量。该方法使用含有添加的增白剂和矫光剂的镀铜电解质。第一铜层以低电流密度电镀，由高投掷功率提供良好的覆盖。高长宽比的开口用相当厚度的均匀的高质量铜涂层覆盖。在电镀期间，增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。任选地，在电镀电流停止的短暂停留期间，增白剂在这些区域中补充。接下来，施加高电流密度，由此填充开口并且以高沉积速率在其上沉积附加的铜。高电流密度沉积的益处在于开口中矫正剂化学品的消耗增加了开口底部的铜的生长速率，从而有利于从下到上生长。这避免了在开口中形成空隙。通过高电流密度步骤，当该方法应用于双镶嵌冶金的形成时，实现了最大的生产效率。

22. 发明申请

US20100230816A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20100230816A1
公开(公告)日：2010-09-16
申请号：US12787559
申请日：2010-05-26
申请人： Hung-Wen Su , Shih-Wei Chou , Ming-Hsing Tsai
发明人： Hung-Wen Su , Shih-Wei Chou , Ming-Hsing Tsai
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76856 , H01L21/76888 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.
摘要翻译：提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。提供了一种半导体器件，包括衬底。其中具有至少一个导电特征的电介质层覆盖在衬底上。绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

23. 发明授权

US07597787B2 Methods and apparatuses for electrochemical deposition 有权
标题翻译：电化学沉积的方法和装置
公开(公告)号：US07597787B2
公开(公告)日：2009-10-06
申请号：US11072137
申请日：2005-03-04
申请人： Hung-Wen Su , Ming-Hsing Tsai
发明人： Hung-Wen Su , Ming-Hsing Tsai
IPC分类号： C25D3/06
CPC分类号： C25D17/001 , C25D17/005 , H01L21/2885 , H01L21/76841
摘要： Methods and apparatuses for electrochemically depositing a metal layer onto a substrate. An electrochemical deposition apparatus comprises a substrate holder assembly including a substrate chuck and a relatively soft cathode contact ring. The cathode contact ring comprises an inner portion and an outer portion, wherein the inner portion directly contacts the substrate. An anode is disposed in an electrolyte container. A power supply connects the substrate holder assembly and the anode.
摘要翻译：将金属层电化学沉积到基底上的方法和装置。一种电化学沉积设备包括一个衬底保持器组件，该衬底保持器组件包括衬底卡盘和相对软的阴极接触环阴极接触环包括内部部分和外部部分，其中内部部分直接接触基板。阳极设置在电解质容器中。电源连接衬底保持器组件和阳极。

24. 发明授权

US07026244B2 Low resistance and reliable copper interconnects by variable doping 有权
标题翻译：低电阻和可靠的铜互连可变掺杂
公开(公告)号：US07026244B2
公开(公告)日：2006-04-11
申请号：US10637105
申请日：2003-08-08
申请人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
发明人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
IPC分类号： H01C23/48
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
摘要翻译：提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层金属合金互连件均保持材料均匀性。

25. 发明申请

US20060054508A1 Process for rendering metal corrosion-resistant in electrochemical metal deposition 审中-公开
标题翻译：在电化学金属沉积中使金属耐腐蚀的方法
公开(公告)号：US20060054508A1
公开(公告)日：2006-03-16
申请号：US10943744
申请日：2004-09-16
申请人： Ming-Wei Lin , Ming-Hsing Tsai
发明人： Ming-Wei Lin , Ming-Hsing Tsai
IPC分类号： C25D3/48 , C25D3/38 , C25D5/48
CPC分类号： H01L21/2885 , C25D3/02 , C25D3/38 , H01L21/7684
摘要： A new and improved method for electroplating a metal onto a substrate in such a manner as to render the metal essentially corrosion-resistant during subsequent substrate processing such as chemical mechanical polishing. The process involves incorporating nitrogen into the metal as the metal is electroplated onto the substrate. The process includes preparing the electroplating bath, placing a leveler chemical containing nitrogen in the prepared bath, circulating the leveler chemical throughout the bath and then electroplating the metal on the substrate. In a preferred embodiment, alkyl polyamide, alkyl amine, alkyl amine oxide or thiourea with molecular weight ranging from 100˜1,000,000 is used as the leveler chemical.
摘要翻译：一种新的和改进的方法，用于将金属电镀到基底上，使得金属在随后的基底处理（例如化学机械抛光）中基本上具有耐腐蚀性。该方法包括在将金属电镀到基底上时将氮掺入金属中。该方法包括制备电镀浴，将准备好的浴中含有氮的矫正剂化学品放置在整个浴中，使整平剂化学品循环，然后将金属电镀在基底上。在优选的实施方案中，使用分子量为100〜1,000,000的烷基聚酰胺，烷基胺，烷基氧化胺或硫脲作为矫光剂。

26. 发明授权

US06479389B1 Method of doping copper metallization 有权
标题翻译：掺杂铜金属化方法
公开(公告)号：US06479389B1
公开(公告)日：2002-11-12
申请号：US09412632
申请日：1999-10-04
申请人： Ming-Hsing Tsai , Sheng Hsiang Chen
发明人： Ming-Hsing Tsai , Sheng Hsiang Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76877 , H01L21/76886
摘要： This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.
摘要翻译：本发明描述了形成铜合金膜的两种新方法。在本发明的第一实施例中，铜合金膜的物理气相沉积（PVD）或溅射之后是纯铜层的化学气相沉积（CVD）或电化学沉积（ECD）。在本发明的第二实施例中，化学气相沉积（CVD）或电化学沉积（ECD）沉积一层纯铜，然后进行物理气相沉积（PVD）或铜合金膜的溅射。在这些方法的另一个实施方案中，特殊的分开的低温退火步骤遵循所述方法以增强铜合金的形成。通过上述两种沉积技术，可以用铜腐蚀和电迁移合金填充高纵横比通孔和沟槽。

27. 发明授权

US06420258B1 Selective growth of copper for advanced metallization 有权
标题翻译：铜的选择性增长用于高级金属化
公开(公告)号：US06420258B1
公开(公告)日：2002-07-16
申请号：US09434564
申请日：1999-11-12
申请人： Sheng Hsiung Chen , Ming-Hsing Tsai
发明人： Sheng Hsiung Chen , Ming-Hsing Tsai
IPC分类号： H01L214763
CPC分类号： H01L21/76879
摘要： A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By these techniques, high aspect ratio trenches can be filled with copper without the problem of dishing. A special, selective electrochemical deposition (ECD) of copper metal is utilized taking place only on the seed layer in the trench. This auto-plating or “plate-up” occurs only in the trench and provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects. The selective plating of copper provides a robust copper film that is easily removed by subsequent chemical mechanical polish (CMP) and tends to be more uniform and free of the usual defects associated with CMP films.
摘要翻译：一种新颖且改进的制造集成电路的方法，其中通过物理气相沉积（PVD），化学机械抛光（CMP）和电化学铜沉积（ECD）技术的组合形成特殊的铜膜。本发明的方法有效地利用几个工艺步骤，导致更少的处理时间，更低的成本和更高的器件可靠性。通过这些技术，可以用铜填充高纵横比沟槽，而不会出现凹陷的问题。仅在沟槽中的种子层上使用铜金属的特殊的选择性电化学沉积（ECD）。这种自动电镀或“平板化”仅发生在沟槽中，并且在沟槽周边和沟槽的细铜金属覆盖层周围提供良好的密封以用于随后的鲁棒互连。铜的选择性电镀提供了坚固的铜膜，其易于通过后续的化学机械抛光（CMP）去除，并且趋向于更均匀并且没有与CMP膜相关的常见缺陷。

28. 发明授权

US09269612B2 Mechanisms of forming damascene interconnect structures 有权
标题翻译：形成镶嵌互连结构的机制
公开(公告)号：US09269612B2
公开(公告)日：2016-02-23
申请号：US13434691
申请日：2012-03-29
申请人： Chien-An Chen , Wen-Jiun Liu , Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
发明人： Chien-An Chen , Wen-Jiun Liu , Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76819 , H01L21/76834 , H01L21/76843 , H01L21/76847 , H01L21/76849 , H01L21/7685 , H01L21/76864 , H01L21/76882 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.
摘要翻译：互连结构包括第一沟槽和第二沟槽。第二沟槽比第一沟槽宽。这两个沟槽都带有扩散阻挡层，并且第一导电层沉积在扩散阻挡层上。在第一导电层上沉积金属覆盖层。第二导电层沉积在第二沟槽中的金属覆盖层上。

29. 发明授权

US09123781B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09123781B2
公开(公告)日：2015-09-01
申请号：US12787559
申请日：2010-05-26
申请人： Hung-Wen Su , Shih-Wei Chou , Ming-Hsing Tsai
发明人： Hung-Wen Su , Shih-Wei Chou , Ming-Hsing Tsai
IPC分类号： H01L21/00 , H01L21/768 , H01L21/285
CPC分类号： H01L23/528 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76856 , H01L21/76888 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.
摘要翻译：提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。提供了一种半导体器件，包括衬底。其中具有至少一个导电特征的电介质层覆盖在衬底上。绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

30. 发明授权

US08053892B2 Low resistance and reliable copper interconnects by variable doping 有权
标题翻译：低电阻和可靠的铜互连可变掺杂
公开(公告)号：US08053892B2
公开(公告)日：2011-11-08
申请号：US11341827
申请日：2006-01-27
申请人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
发明人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
摘要翻译：提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层金属合金互连件均保持材料均匀性。

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