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1. 发明授权

US5714803A Low-profile removable ball-grid-array integrated circuit package 失效
标题翻译：薄型可拆卸球栅阵列集成电路封装
公开(公告)号：US5714803A
公开(公告)日：1998-02-03
申请号：US508919
申请日：1995-07-28
申请人： Daniel G. Queyssac
发明人： Daniel G. Queyssac
IPC分类号： H01L23/32 , H01L23/48 , H01L23/498 , H05K3/32 , H05K7/10 , H01C23/48 , H01C23/52 , H01C29/40
CPC分类号： H05K7/1061 , H01L23/32 , H01L23/49816 , H01L24/72 , H05K3/325 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： An integrated circuit package has leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated circuit package is placed in a frame and held to the printed circuit board with a clamp or with a screw.
摘要翻译：集成电路封装具有用导电热塑性粘合剂附着到基板上的无引线焊球。无引线焊球优选由铜 - 镍 - 金合金制成。导电性热塑性材料优选为银填充型。集成电路封装放置在框架中，并用夹具或螺丝固定在印刷电路板上。

2. 发明授权

US07026244B2 Low resistance and reliable copper interconnects by variable doping 有权
标题翻译：低电阻和可靠的铜互连可变掺杂
公开(公告)号：US07026244B2
公开(公告)日：2006-04-11
申请号：US10637105
申请日：2003-08-08
申请人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
发明人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
IPC分类号： H01C23/48
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
摘要翻译：提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层金属合金互连件均保持材料均匀性。

3. 发明授权

US06878465B2 Under bump metallurgy for Lead-Tin bump over copper pad 有权
标题翻译：铅焊锡凸点焊接在铜焊盘上
公开(公告)号：US06878465B2
公开(公告)日：2005-04-12
申请号：US10608407
申请日：2003-06-26
申请人： Peter K. Moon , Zhiyong Ma , Madhav Datta
发明人： Peter K. Moon , Zhiyong Ma , Madhav Datta
IPC分类号： B23K1/00 , B23K1/20 , C22C21/06 , H01L21/60 , H01L23/485 , B32B15/02 , B32B15/04 , B32B15/20 , H01C23/48
CPC分类号： H01L24/03 , B23K1/0016 , B23K1/20 , B23K2101/42 , C22C21/06 , H01L24/11 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1147 , H01L2224/13023 , H01L2224/131 , H01L2924/00013 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/0105 , H01L2924/01072 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , Y10T428/12486 , Y10T428/12701 , Y10T428/12736 , Y10T428/12743 , Y10T428/1275 , Y10T428/12806 , Y10T428/12903 , Y10T428/265 , H01L2224/13099
摘要： The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium.The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.
摘要翻译：本发明描述了一种方法，包括提供组件，该组件具有接合垫; 在所述部件上形成钝化层; 在钝化层中形成通孔以露出接合焊盘; 以及在钝化层上，在通孔中以及焊接垫上形成凸块下的金属（UBM），其中UBM包括铝和镁的合金。本发明还描述了一种凸起下冶金（UBM），其包括下层，下层包括铝和镁的合金; 以及位于下层上方的上层。

4. 发明授权

US6127732A Semiconductor device having high aspect ratio contacts 失效
标题翻译：具有高纵横比接触的半导体器件
公开(公告)号：US6127732A
公开(公告)日：2000-10-03
申请号：US059671
申请日：1998-04-13
申请人： Shubneesh Batra , Gurtej Sandhu
发明人： Shubneesh Batra , Gurtej Sandhu
IPC分类号： H01L21/768 , H01L23/532 , H01C23/48
CPC分类号： H01L23/53214 , H01L21/76877 , H01L21/76882 , H01L2924/0002
摘要： Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.
摘要翻译：在半导体工艺中将杂质添加到导体层中以防止形成空隙并促进接触的完全填充。杂质降低导体层的熔点和表面张力，从而改善回流步骤期间的填充特性。杂质可以在该过程中的任何时间加入，包括在导体沉积和/或回流期间。

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