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21. 发明授权

US5024956A Method of manufacturing a semiconductor device including mesa bipolar transistor with edge contacts 失效
标题翻译：制造包括具有边缘触点的台面双极晶体管的半导体器件的方法
公开(公告)号：US5024956A
公开(公告)日：1991-06-18
申请号：US534774
申请日：1990-06-07
申请人： Johannes W. A. Van Der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Johannes W. A. Van Der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L29/73 , H01L21/331 , H01L29/423 , H01L29/732
CPC分类号： H01L29/42304 , H01L29/7325 , Y10S148/125
摘要： A method of manufacturing a semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by said oxide strip (12A) is situated between said first and said second zones and located below said oxide strip (12A).

22. 发明授权

US4937202A Method of manufacturing field effect transistors having self-registering source and drain regions to minimize capacitances 失效
标题翻译：制造具有自对准源极和漏极区域的场效应晶体管的方法，以最小化电容
公开(公告)号：US4937202A
公开(公告)日：1990-06-26
申请号：US272660
申请日：1988-11-17
申请人： Henricus G. R. Maas
发明人： Henricus G. R. Maas
IPC分类号： H01L27/10 , H01L21/205 , H01L21/285 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/45 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/28525 , H01L27/10823 , H01L29/456
摘要： A field effect transistor is made with a source and drain which are utilized partly as a semiconductor region in a semiconductor body, and partly as a portion of a deposited epitaxial layer. A recess is formed into a substrate of the semiconductor body between the source and drain, and a channel region underlies the recess in the substrate. As a result of this construction, the channel length is independent of variations in the thickness of the epitaxial layer, and the stray capacitances from source and drain to the substrate are small. Moreover, a conductor pattern, separated from the epitaxial layer by an insulating layer, may extend to be on the connection zones of the source and drain, which involves a high packing density. The epitaxial layer, moreover, comprises extra wiring tracks. This gives a greater freedom in design.

23. 发明授权

US4717689A Method of forming semimicron grooves in semiconductor material 失效
标题翻译：在半导体材料中形成半圆形槽的方法
公开(公告)号：US4717689A
公开(公告)日：1988-01-05
申请号：US776330
申请日：1985-09-16
申请人： Henricus G. R. Maas , Johannes A. Appels
发明人： Henricus G. R. Maas , Johannes A. Appels
IPC分类号： H01L21/302 , H01L21/033 , H01L21/3065 , H01L21/762 , H01L21/76
CPC分类号： H01L21/033 , H01L21/762 , Y10S438/947
摘要： On a layer having a stepped relief, such as a masking layer (4) having openings (5) on a substrate region, (2) a first layer (6) is provided, which, while maintaining the stepped relief, is covered by a second masking layer (8) and a convertible layer (9). By conversion of the convertible layer (9) (by means of ion implantation, oxidation, silicidation) this layer becomes selectively etchable. After removal of the non-converted parts, an intermediate mask (8) is formed with an opening in the second masking layer (8) along the edge of a depression (7). By means of the mask (8) thus obtained, grooves (11) are formed by anisotropic etching in the first layer (6) and in the subjacent substrate region (2) if required. When grooves are formed in a substrate region (2) of semiconductor material, these grooves may be filled with oxide (25) for forming insulated regions. If a first layer (6) of polycrystalline silicon is used on a substrate region (2) of silicon, this layer (6) can serve as a doping source and a connection, respectively. Thus, various kinds of transistors (MOSFET and bipolar transistors) can be manufactured. The second masking layer (8) and the convertible layer (9) may be realized, if required, as a single layer (65).
摘要翻译：在具有阶梯式浮雕的层上，例如在基板区域上具有开口（5）的掩模层（4），（2）第一层（6），其在保持阶梯式浮雕的同时被第二掩模层（8）和可转换层（9）。通过可转换层（9）（通过离子注入，氧化，硅化）的转化，该层变得可选择性地蚀刻。在去除未转换部件之后，沿着凹部（7）的边缘，在第二掩模层（8）中形成具有开口的中间掩模（8）。通过如此获得的掩模（8），如果需要，在第一层（6）和下层衬底区域（2）中通过各向异性蚀刻形成凹槽（11）。当在半导体材料的衬底区域（2）中形成沟槽时，这些沟槽可以填充用于形成绝缘区域的氧化物（25）。如果在硅的衬底区域（2）上使用多晶硅的第一层（6），则该层（6）可以分别用作掺杂源和连接。因此，可以制造各种晶体管（MOSFET和双极晶体管）。如果需要，可以将第二掩蔽层（8）和可转换层（9）实现为单层（65）。

24. 发明授权

US06177295B1 Method of manufacturing semiconductor devices with “chip size package” 有权
标题翻译：使用“芯片尺寸封装”制造半导体器件的方法
公开(公告)号：US06177295B1
公开(公告)日：2001-01-23
申请号：US09268259
申请日：1999-03-15
申请人： Mark A. De Samber , Henricus G. R. Maas
发明人： Mark A. De Samber , Henricus G. R. Maas
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L24/02 , H01L2224/0401 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/00
摘要： A method of manufacturing enveloped semiconductor devices, in which use is made of a slice of a semiconductor material which is provided on its first side with an intermediate layer of an insulating material on which a top layer of a semiconductor material is formed, semiconductor elements are formed in the top layer, paths of the slice's surface situated on this side being left clear between the semiconductor elements, and the top layer is removed from the insulating intermediate layer at the location of the free paths. A metallization with connection electrodes extending as far as the free paths are formed on the first side of the slice, the slice is glued with its first side onto a transparent insulating supporting body, semiconductor material is removed from the second side of the slice facing away from the first side, and the slice thus reduced in thickness is provided on its second side with a layer of an insulating material. Grooves are formed in the supporting body, at the location of the free paths, which grooves intersect the connection electrodes of the metallization and extend into the layer of insulating material provided on the second side of the slice, conductor tracks are formed on the supporting body, which extend in the grooves so as to make contact with the connection electrodes intersected in the grooves, and the slice is divided, along the grooves, into separate semiconductor devices enveloped by the supporting body and the insulating layer provided on the second side.
摘要翻译：一种制造包封半导体器件的方法，其中使用半导体材料的切片，其在其第一侧上设置有形成半导体材料的顶层的绝缘材料的中间层，半导体元件形成在顶层中，位于该侧的切片表面的路径在半导体元件之间保持透明，并且在自由路径的位置处将顶层从绝缘中间层移除。在切片的第一侧上形成有连接电极延伸至自由路径的金属化，其切片与其第一侧胶合到透明绝缘支撑体上，将半导体材料从切片的第二侧面朝外移除并且在其第二侧上设置有由绝缘材料层构成的厚度减小的切片。凹槽形成在支撑体中，在自由路径的位置处，该沟槽与金属化的连接电极相交并且延伸到设置在切片的第二侧上的绝缘材料层，导体轨道形成在支撑体上其在沟槽中延伸以与在沟槽中相交的连接电极接触，并且该切片沿着凹槽被分割成由支撑体包围的分离的半导体器件和设置在第二侧上的绝缘层。

25. 发明授权

US5268313A Method of manufacturing a semiconductor device having a spacer 失效
标题翻译：制造具有间隔物的半导体器件的方法
公开(公告)号：US5268313A
公开(公告)日：1993-12-07
申请号：US820454
申请日：1992-01-13
申请人： Henricus G. R. Maas , Armand Pruijmboom , Peter H. Kranen , Johanna M. L. Van Rooij-Mulder , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Henricus G. R. Maas , Armand Pruijmboom , Peter H. Kranen , Johanna M. L. Van Rooij-Mulder , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L21/306 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/60 , H01L29/10 , H01L29/73 , H01L29/732 , H01L21/265
CPC分类号： H01L21/76897 , H01L21/28525 , H01L29/1004 , H01L29/66272 , H01L29/66287 , H01L29/732 , Y10S148/01 , Y10S148/102
摘要： A method of manufacturing a semiconductor device whereby an spacer is formed from a second layer in a fully self-registering manner after a layer portion of a first layer has been formed. For this purpose, the second layer and a masking layer are provided in that order, which masking layer has a greater thickness next to the layer portion than above it. The portion of the second layer situated above the layer portion and the spacer to be formed is then exposed in that the masking layer is etched back over at least substantially its entire surface. A portion of the masking layer then remains next to the layer portion, which masking layer portion is sufficiently thick for adequately protecting the subjacent portion of the second layer against the treatment which is subsequently carried out and by which the etching resistance of at least the top layer of the exposed portion of the second layer is increased. The non-treated portion of the second layer is then selectively etched relatively to the treated portion in order to form the spacer.

26. 发明授权

US5008209A Method of manufacturing a semiconductor device including outdiffusion from polysilicon rims 失效
标题翻译：制造半导体器件的方法，其包括从多晶硅边缘扩散
公开(公告)号：US5008209A
公开(公告)日：1991-04-16
申请号：US463183
申请日：1990-01-10
申请人： Johannes A. Appels , Henricus G. R. Maas
发明人： Johannes A. Appels , Henricus G. R. Maas
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/06 , H01L29/73 , H01L29/78
CPC分类号： H01L21/76838 , H01L23/522 , H01L23/53271 , H01L2924/0002 , Y10S148/131
摘要： A method of manufacturing a semiconductor device is set forth using anisotropic etching techniques, such as plasma etching and reactive ion etching to obtain interconnection patterns having accurately defined rims. Various different kinds of transistors can be manufacturing in the same semiconductor body using these techniques.
摘要翻译：使用诸如等离子体蚀刻和反应离子蚀刻之类的各向异性蚀刻技术来提供制造半导体器件的方法，以获得具有精确定义的边缘的互连图案。可以使用这些技术在相同的半导体主体中制造各种不同种类的晶体管。

27. 发明授权

US4907049A Charge-coupled semiconductor device having an improved electrode structure 失效
标题翻译：具有改进的电极结构的电荷耦合半导体器件
公开(公告)号：US4907049A
公开(公告)日：1990-03-06
申请号：US385928
申请日：1989-07-27
申请人： Jan W. Slotboom , Henricus G. R. Maas , Kazimierz Osinki , Geert J. T. Davids
发明人： Jan W. Slotboom , Henricus G. R. Maas , Kazimierz Osinki , Geert J. T. Davids
IPC分类号： H01L29/762 , H01L21/339 , H01L27/10 , H01L29/423 , H01L29/76 , H01L29/772
CPC分类号： H01L29/66954 , H01L29/42396
摘要： A charge-coupled semiconductor device has a plurality of silicon electrodes for storing and transporting information-carrying charge, which electrodes are located on an insulating layer and are mutually separated by grooves having a width of at most 1 .mu.m. According to the invention, transfer electrodes are arranged in the grooves, these electrodes being coplanar with the remaining electrodes. The thickness of the insulating layer under the transfer electrodes is substantially equal to that under the storage electrodes. The invention also relates to a method of manufacturing a semiconductor device having such an electrode system.
摘要翻译：电荷耦合半导体器件具有用于存储和传送信息传送电荷的多个硅电极，这些电极位于绝缘层上并且由宽度至多为1μm的沟槽相互分离。根据本发明，转移电极布置在凹槽中，这些电极与剩余的电极共面。传输电极下面的绝缘层的厚度基本上等于存储电极下方的厚度。本发明还涉及制造具有这种电极系统的半导体器件的方法。

28. 发明授权

US4981806A Method of manufacturing a semiconductor device 失效
公开(公告)号：US4981806A
公开(公告)日：1991-01-01
申请号：US504194
申请日：1990-04-03
申请人： Henricus G. R. Maas , Roland A. Van ES , Johannes W. A. Van Der Velden , Peter H. Kranen
发明人： Henricus G. R. Maas , Roland A. Van ES , Johannes W. A. Van Der Velden , Peter H. Kranen
IPC分类号： H01L29/73 , H01L21/28 , H01L21/285 , H01L21/3215 , H01L21/331 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/32155 , Y10S148/01 , Y10S148/011 , Y10S148/096 , Y10S438/911
摘要： A device area (16) is defined in a semiconductor body (10) by forming at one major surface (12, 12a) of the body a step (11) having a side wall (11a) and top surface (11b) bounding the device area 16. A silicon layer (13) is deposited so as to cover the side wall (11a) and top surface (11b) of the step and an adjoining lower surface area (12c). Dopant impurities are introduced so that the side wall silicon region (13a) is shielded from the dopant impurities and the undoped side wall silicon region (13a) is later removed by selective etching. The silicon region (13c) on the lower surface area (12a) adjoining the step (11) is masked and the silicon region (13a) on the top surface (11b) at the step (11) removed to leave the doped silicon region (13c) on the one major surface (12a) for contacting a device region (29), for example the base region of a transistor, of the device area.

29. 发明授权

US4825267A Field effect transistor having self-registering source and drain regions to minimize capacitances 失效
标题翻译：场效应晶体管具有自对准源极和漏极区域以最小化电容
公开(公告)号：US4825267A
公开(公告)日：1989-04-25
申请号：US721123
申请日：1985-04-08
申请人： Henricus G. R. Maas
发明人： Henricus G. R. Maas
IPC分类号： H01L27/10 , H01L21/205 , H01L21/285 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/45 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/28525 , H01L27/10823 , H01L29/456
摘要： A field effect transistor is formed with a source and drain which are realized partly as a semiconductor region and a semiconductor body, and partly as a portion of a deposited epitaxial layer. A recess is formed into a substrate of the semiconductor body between the source and drain, and a channel region underlies the recess in the substrate. As a result of this construction, the channel length is independent of variations in the thickness of the epitaxial layer, and the stray capacitances from source and drain to the substrate are small. Moreover, a conductor pattern, separated from the epitaxial layer by an insulating layer, may extend to be on the connection zones of the source and drain, which involves a high packing density. The epitaxial layer, moreover, comprises extra wiring tracks. This gives a great freedom in design.
摘要翻译：场效应晶体管形成有源极和漏极，其部分地被实现为半导体区域和半导体本体，并且部分地被实现为沉积的外延层的一部分。在源极和漏极之间形成半导体本体的衬底中的凹槽，并且沟道区域位于衬底中的凹部下方。作为这种结构的结果，沟道长度与外延层的厚度的变化无关，并且从源极和漏极到衬底的杂散电容很小。此外，通过绝缘层与外延层分离的导体图案可以延伸到源极和漏极的连接区上，其包括高堆积密度。此外，外延层包括额外的布线轨道。这给设计带来了很大的自由。

30. 发明授权

US4689872A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4689872A
公开(公告)日：1987-09-01
申请号：US771930
申请日：1985-09-03
申请人： Johannes A. Appels , Henricus G. R. Maas
发明人： Johannes A. Appels , Henricus G. R. Maas
IPC分类号： H01L29/78 , H01L21/033 , H01L21/225 , H01L21/331 , H01L21/336 , H01L23/532 , H01L29/73 , H01L29/732 , H01L21/22 , H01L21/265 , H01L21/318
CPC分类号： H01L29/66272 , H01L21/0337 , H01L21/2257 , H01L23/53271 , H01L2924/0002 , Y10S148/011 , Y10S148/051 , Y10S148/103 , Y10S438/911
摘要： For providing semiconductor zones (16, 18, 26) and contact metallization (19, 27) within an opening (9) in a self-registered manner, which opening is provided along its edge with polycrystalline connection parts (10) separated by an insulating material (15) from the metallization (19, 27), a protective layer (11) is formed which is maintained within the opening (9)until within this opening (9) the connection parts (10) are formed by anisotropic etching from a uniform layer of polycrystalline semiconductor material (10). The method is suitable for the manufacture of both bipolar transistors and field effect transistors.
摘要翻译：为了以自我注册的方式在开口（9）内提供半导体区域（16,18,26）和接触金属化（19,27），所述开口沿着其边缘设置有由绝缘体分隔的多晶连接部分（10）从金属化（19,27）的材料（15）形成保护层（11），其保持在开口（9）内，直到在该开口（9）内，连接部分（10）通过各向异性蚀刻从均匀的多晶半导体材料层（10）。该方法适用于制造双极晶体管和场效应晶体管。

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