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1. 发明授权

US4969026A Mesa bipolar transistor with edge contacts 失效
标题翻译：具有边缘触点的Mesa双极晶体管
公开(公告)号：US4969026A
公开(公告)日：1990-11-06
申请号：US506484
申请日：1990-04-06
申请人： Johannes W. A. Van der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Johannes W. A. Van der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L29/73 , H01L21/331 , H01L29/423 , H01L29/732
CPC分类号： H01L29/42304 , H01L29/7325 , Y10S148/125
摘要： A semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by the oxide strip (12A) is situated between the first and the second zones and located below the oxide strip (12A). The invention further relates to a method of manufacturing this device.

2. 发明授权

US5024956A Method of manufacturing a semiconductor device including mesa bipolar transistor with edge contacts 失效
标题翻译：制造包括具有边缘触点的台面双极晶体管的半导体器件的方法
公开(公告)号：US5024956A
公开(公告)日：1991-06-18
申请号：US534774
申请日：1990-06-07
申请人： Johannes W. A. Van Der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Johannes W. A. Van Der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L29/73 , H01L21/331 , H01L29/423 , H01L29/732
CPC分类号： H01L29/42304 , H01L29/7325 , Y10S148/125
摘要： A method of manufacturing a semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by said oxide strip (12A) is situated between said first and said second zones and located below said oxide strip (12A).

3. 发明授权

US5268313A Method of manufacturing a semiconductor device having a spacer 失效
标题翻译：制造具有间隔物的半导体器件的方法
公开(公告)号：US5268313A
公开(公告)日：1993-12-07
申请号：US820454
申请日：1992-01-13
申请人： Henricus G. R. Maas , Armand Pruijmboom , Peter H. Kranen , Johanna M. L. Van Rooij-Mulder , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Henricus G. R. Maas , Armand Pruijmboom , Peter H. Kranen , Johanna M. L. Van Rooij-Mulder , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L21/306 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/60 , H01L29/10 , H01L29/73 , H01L29/732 , H01L21/265
CPC分类号： H01L21/76897 , H01L21/28525 , H01L29/1004 , H01L29/66272 , H01L29/66287 , H01L29/732 , Y10S148/01 , Y10S148/102
摘要： A method of manufacturing a semiconductor device whereby an spacer is formed from a second layer in a fully self-registering manner after a layer portion of a first layer has been formed. For this purpose, the second layer and a masking layer are provided in that order, which masking layer has a greater thickness next to the layer portion than above it. The portion of the second layer situated above the layer portion and the spacer to be formed is then exposed in that the masking layer is etched back over at least substantially its entire surface. A portion of the masking layer then remains next to the layer portion, which masking layer portion is sufficiently thick for adequately protecting the subjacent portion of the second layer against the treatment which is subsequently carried out and by which the etching resistance of at least the top layer of the exposed portion of the second layer is increased. The non-treated portion of the second layer is then selectively etched relatively to the treated portion in order to form the spacer.

4. 发明授权

US4894702A High efficiency, small geometry semiconductor devices 失效
标题翻译：高效率，小几何半导体器件
公开(公告)号：US4894702A
公开(公告)日：1990-01-16
申请号：US163428
申请日：1988-03-03
申请人： Henricus G. R. Maas , Johannes W. A. Van Der Velden , Peter H. Kranen , Albertus T. M. Van De Goor , Date J. W. Noorlag
发明人： Henricus G. R. Maas , Johannes W. A. Van Der Velden , Peter H. Kranen , Albertus T. M. Van De Goor , Date J. W. Noorlag
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/336 , H01L21/763 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/732 , H01L29/735
CPC分类号： H01L29/735 , H01L21/28525 , H01L21/763 , H01L29/0653 , H01L29/41766 , H01L29/66272 , H01L29/66636 , H01L29/732 , H01L29/78
摘要： A semiconductor device comprising a first region, which is laterally bounded by a second region comprising a countersunk oxide layer and a highly doped polycrystalline silicon layer, which is disposed thereon and is covered by an oxide layer partly countersunk into it. The side edge of the polysilicon layer adjoins a contact zone, which is obtained by diffusion therefrom and is connected via a current path to a zone of a semiconductor circuit element. The upper side of the polysilicon layer is located at a higher level than that of the first region and the contact zone is connected to the said zone of the semiconductor circuit element via an intermediate region located in the first region below the second oxide layer and having a lower doping than the contact zone.

5. 发明授权

US4981806A Method of manufacturing a semiconductor device 失效
公开(公告)号：US4981806A
公开(公告)日：1991-01-01
申请号：US504194
申请日：1990-04-03
申请人： Henricus G. R. Maas , Roland A. Van ES , Johannes W. A. Van Der Velden , Peter H. Kranen
发明人： Henricus G. R. Maas , Roland A. Van ES , Johannes W. A. Van Der Velden , Peter H. Kranen
IPC分类号： H01L29/73 , H01L21/28 , H01L21/285 , H01L21/3215 , H01L21/331 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/32155 , Y10S148/01 , Y10S148/011 , Y10S148/096 , Y10S438/911
摘要： A device area (16) is defined in a semiconductor body (10) by forming at one major surface (12, 12a) of the body a step (11) having a side wall (11a) and top surface (11b) bounding the device area 16. A silicon layer (13) is deposited so as to cover the side wall (11a) and top surface (11b) of the step and an adjoining lower surface area (12c). Dopant impurities are introduced so that the side wall silicon region (13a) is shielded from the dopant impurities and the undoped side wall silicon region (13a) is later removed by selective etching. The silicon region (13c) on the lower surface area (12a) adjoining the step (11) is masked and the silicon region (13a) on the top surface (11b) at the step (11) removed to leave the doped silicon region (13c) on the one major surface (12a) for contacting a device region (29), for example the base region of a transistor, of the device area.

6. 发明授权

US5039623A Method of manufacturing a semiconductor device 失效
公开(公告)号：US5039623A
公开(公告)日：1991-08-13
申请号：US504187
申请日：1990-04-03
申请人： Henricus G. R. Maas , Roland A. Van Es , Johannes W. A. Van Der Velden
发明人： Henricus G. R. Maas , Roland A. Van Es , Johannes W. A. Van Der Velden
IPC分类号： H01L29/73 , H01L21/225 , H01L21/28 , H01L21/285 , H01L21/3215 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/28525 , H01L21/32155 , Y10S148/01 , Y10S148/031 , Y10S148/044
摘要： A semiconductor body (10) has at one major surface (15) a step (14) defining a device area (13) of the semiconductor body above a buried region (12) provided within the semiconductor body (10). A protective insulating layer (24) is provided on a side wall (14a) of the step (14) and an insulating region (22) on an area (15a) of the one major surface adjoining the side wall (14a) of the step. Silicon is deposited over the one surface (15) with the anti-oxidation layer (24) on the side wall (14a) of the step (14) to define over the area (15a) of the one surface (15) an intermediate silicon region (23c) which is isolated from the side wall (14a) of the step and which leaves a window area (14'a) of the side wall (14a) exposed. The protective insulating layer (24a) is then removed from the window area (14'a) of the side wall (14a). A silicon region (25c) doped with impurities is defined over the insulating region (22) and adjoining the side wall (14a) of the step (14), and the dopant impurities caused to diffuse from the doped silicon region (25c) into the device area (13) via the window area (14'a) to define a contact region (28) for contacting a device region (29) within the device area (13).

7. 发明授权

US06172408B2 Radiation-sensitive semiconductor device and method of manufacturing same 失效
标题翻译：辐射敏感半导体器件及其制造方法
公开(公告)号：US06172408B2
公开(公告)日：2001-01-09
申请号：US09273282
申请日：1999-03-19
申请人： Myron W. L. Seto , Stienke De Jager , Henricus G. R. Maas
发明人： Myron W. L. Seto , Stienke De Jager , Henricus G. R. Maas
IPC分类号： H01L31075
CPC分类号： H01L31/1892 , H01L31/022408 , H01L31/02327 , H01L31/105 , Y02E10/50
摘要： The invention relates to a radiation-sensitive device comprising a thin radiation-sensitive element (2), in particular a thin photodiode (2). The device includes a substrate (1) on which a photodiode (2) is provided. The surface (5) of the photodiode serves as a semi-pervious mirror (5) through which the radiation (100) enters; a reflecting layer (6) situated between the photodiode (2) and the substrate (1) also serves as a mirror (6). As a result, a so-called resonant cavity effect is possible, resulting, inter alia, in wavelength selectivity of the device. The known device has insufficient wavelength selectivity, which, in addition, cannot readily be set in an accurate and reproducible manner. A device in accordance with the invention is characterized in that the reflecting layer (6) is a metal layer (6) and in that the photodiode (2) is secured to the substrate (1) by means of an adhesive layer (7). By virtue of the high reflectivity of one (6) of the two mirrors (5, 6), the device has a great wavelength selectivity which, in addition, can be readily set in an accurate and reproducible manner. The adhesive layer (7) does not only enable the photodiode (7) to be secured to a substrate (1), which does not have to be a semiconductor substrate, but, this method of securing also enables a very attractive manufacturing method for the entire device to be achieved. A device in accordance with the invention can be advantageously used as a detector in a heterodyne or multiplex optical communication system or in an optical disc system.
摘要翻译：本发明涉及一种包括薄辐射敏感元件（2），特别是薄光电二极管（2）的辐射敏感器件。该器件包括其上设置有光电二极管（2）的衬底（1）。光电二极管的表面（5）用作半透明反射镜（5），辐射（100）通过该反射镜进入; 位于光电二极管（2）和基板（1）之间的反射层（6）也用作反射镜（6）。结果，所谓的谐振腔效应是可能的，特别是导致器件的波长选择性。已知的装置具有不充分的波长选择性，另外不能容易地以精确和可再现的方式设置。根据本发明的装置的特征在于反射层（6）是金属层（6）光电二极管（2）通过粘合剂层（7）固定到基底（1）上。由于两个反射镜（5,6）中的一个（6）的高反射率，该器件具有很大的波长选择性，此外，可以容易地以准确和可再现的方式设置。粘合剂层（7）不仅可以使光电二极管（7）固定到不必是半导体基板的基板（1）上，而且这种固定方法也可以使非常有吸引力的制造方法整个设备要实现。根据本发明的装置可以有利地用作外差或多路光通信系统或光盘系统中的检测器。

8. 发明授权

US5221856A Bipolar transistor with floating guard region under extrinsic base 失效
标题翻译：双极晶体管，外部基极具有浮动保护区域
公开(公告)号：US5221856A
公开(公告)日：1993-06-22
申请号：US833599
申请日：1992-02-10
申请人： Ronald Dekker , Martinus C. A. M. Koolen , Henricus G. R. Maas
发明人： Ronald Dekker , Martinus C. A. M. Koolen , Henricus G. R. Maas
IPC分类号： H01L21/225 , H01L21/285 , H01L21/32 , H01L21/3213 , H01L21/3215 , H01L21/331 , H01L21/60 , H01L29/732
CPC分类号： H01L21/76897 , H01L21/2257 , H01L21/28506 , H01L21/28525 , H01L21/32 , H01L21/32134 , H01L21/32155 , H01L29/66242 , H01L29/66272 , H01L29/7325
摘要： A first device region (10) of one conductivity type adjacent one major surface (1a) of a semiconductor body (1) has a relatively highly doped subsidiary region (11) spaced from the one major surface (1a) by a relatively lowly doped subsidiary region (12). A second device region (20) of the opposite conductivity type within the subsidiary region (12) has an intrinsic subsidiary region (21) and an extrinsic subsidiary region (23,24) surrounding the intrinsic subsidiary region (21) forming respective first and second pn junctions (22,25) with the relatively lowly doped subsidiary region (12). A third device region (30) of the one conductivity type is formed within the intrinsic subsidiary region (21) surface (1a). An additional region (60,60',61,62) is provided beneath the extrinsic subsidiary region (23,24) so as to lie within the spread of the depletion region (250) associated with the second pn junction (25) when the first and second pn junction (22,25) are reverse-biassed thereby extending the depletion region (250) beneath the emitter region (30) to cause an increase in the Early voltage (V.sub.eaf) of the device.
摘要翻译：与半导体本体（1）的一个主表面（1a）相邻的一种导电类型的第一器件区域（10）具有相对高度掺杂的辅助区域（11），该区域通过相对低掺杂的子元件与一个主表面（1a）间隔开区域（12）。在辅助区域（12）内具有相反导电类型的第二设备区域（20）具有内部辅助区域（21）和围绕内部辅助区域（21）的外在辅助区域（23,24），形成相应的第一和第二 pn结（22,25）与相对低掺杂的辅助区域（12）。一个导电类型的第三器件区域（30）形成在本征辅助区域（21）表面（1a）内。在外部辅助区域（23,24）的下方提供附加区域（60,60'，61,62），以便当位于与第二pn结（25）相关联的耗尽区域（250）的扩展区内时第一和第二pn结（22,25）被反向偏压，从而将耗尽区（250）延伸到发射极区（30）之下，以引起器件的早期电压（Veaf）的增加。

9. 发明授权

US4574468A Method of manufacturing a semiconductor device having narrow coplanar silicon electrodes 失效
标题翻译：制造具有窄共面硅电极的半导体器件的方法
公开(公告)号：US4574468A
公开(公告)日：1986-03-11
申请号：US657631
申请日：1984-10-04
申请人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
发明人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
IPC分类号： H01L29/762 , H01L21/033 , H01L21/339 , H01L27/10 , H01L29/76 , H01L29/772 , H01L21/90
CPC分类号： H01L29/66954 , H01L21/033
摘要： A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.
摘要翻译：一种制造半导体器件的方法，例如具有窄共面硅电极的SPS存储器。通过将具有亚微米范围宽度的槽或槽（10）蚀刻成多晶硅层（3）形成电极，槽宽度由硅辅助层（5）的氧化边缘（6）限定。电极被氧化硅交替地覆盖，并且由包含氮化硅的层交替地覆盖。根据本发明，由氧化硅（3B，13B）覆盖的电极首先成对互连，于是它们在单独的蚀刻步骤中彼此分离并且设置有自对准的接触窗口（15）。因此，非常窄的电极可以在没有技术问题的情况下接触，并且可以获得非常小的尺寸的存储单元。

10. 发明授权

US06368921B1 Manufacture of trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件的制造
公开(公告)号：US06368921B1
公开(公告)日：2002-04-09
申请号：US09671888
申请日：2000-09-28
申请人： Erwin A. Hijzen , Henricus G. R. Maas , Cornelius E. Timmering
发明人： Erwin A. Hijzen , Henricus G. R. Maas , Cornelius E. Timmering
IPC分类号： H01L2336
CPC分类号： H01L29/66348
摘要： A trench-gate semiconductor device, for example a MOSFET or IGBT, of compact geometry is manufactured with self-aligned masking techniques in a simple process with good reproducibility. The source region (13) of the device is formed by introducing dopant (63) into an area of the body region (15) via a mask window (51a), diffusing the dopant to form a surface region (13b) that extends laterally below the mask (51) at a distance (d) beyond the masking edge (51b) of the window (51a), and then etching the body (10) at the window (51a) to form a trench (20) for the trench-gate (11) with a lateral extent (y) that is determined by the etching of the body (10) at the masking edge (51b) of the window (51a). A portion of the surface region (13b) is left to provide the source region (13) adjacent to the trench (20). The invention permits the etch edge definition for the trench (2) to be better controlled by using the masking edge (51b) of a well-defined mask (51), as compared with the less well defined edges that tend to result from the use of a side-wall extension in prior-art processes.
摘要翻译：具有紧凑几何形状的沟槽栅极半导体器件（例如MOSFET或IGBT）以简单的过程以自调整掩蔽技术制造，具有良好的再现性。通过掩模窗（51a）将掺杂剂（63）引入体区（15）的一个区域中形成器件的源极区（13），使掺杂剂扩散形成横向延伸的表面区域（13b）在窗口（51a）的掩蔽边缘（51b）之外的距离（d）处的掩模（51），然后在窗口（51a）处蚀刻主体（10），以形成用于沟槽门（11）具有通过在窗口（51a）的掩蔽边缘（51b）处对主体（10）的蚀刻确定的横向延伸（y）。留下表面区域（13b）的一部分以提供与沟槽（20）相邻的源极区域（13）。本发明允许通过使用明确定义的掩模（51）的掩模边缘（51b）来更好地控制沟槽（2）的蚀刻边缘定义，与通常由使用导致的较不明确的边缘相比较的现有技术中的侧壁延伸。

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