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21. 发明申请

US20110022773A1 Fine Grained Cache Allocation 有权
标题翻译：细粒度缓存分配
公开(公告)号：US20110022773A1
公开(公告)日：2011-01-27
申请号：US12509752
申请日：2009-07-27
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084 , G06F12/0864 , G06F12/126 , Y02D10/13
摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.
摘要翻译：在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。标签的MSB部分在一组中的高速缓存行之间共享。标签的LSB部分是私有的，每个缓存行一个。该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

22. 发明申请

US20110021346A1 POLYMERIZATION CATALYST COMPOSITION FOR POLYMERIZATION OF ISOPRENE COMPOUND 失效
标题翻译：聚异氰酸酯化合物聚合的聚合催化剂组合物
公开(公告)号：US20110021346A1
公开(公告)日：2011-01-27
申请号：US12897750
申请日：2010-10-04
申请人： Zhaomin HOU , Lixin Zhang
发明人： Zhaomin HOU , Lixin Zhang
IPC分类号： B01J31/18
CPC分类号： C08F36/08 , C08F4/545 , C08F4/52
摘要： 3,4-isoprene-based polymer having high isotacticity can be produced by polymerizing an isoprene compound using a complex represented by the general formula (A) and a catalyst activator: wherein R1 and R2 independently represent an alkyl group, a cyclohexyl group, an aryl group or an aralkyl group; R3 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group, an aralkyl group, an aliphatic, aromatic or cyclic amino group, a phosphino group, a boryl group, an alkylthio or arylthio group, or an alkoxy or aryloxy group; M represents a rare earth element selected from Sc, Y, and La to Lu with promethium (Pm) excluded; Q1 and Q2 independently represent a monoanionic ligand; L represents a neutral Lewis base.
摘要翻译：具有高全同立构规整度的3,4-异戊二烯类聚合物可以通过使用由通式（A）表示的络合物和催化剂活化剂聚合异戊二烯化合物来制备：其中R1和R2独立地表示烷基，环己基，芳基或芳烷基; R3表示烷基，烯基，炔基，芳基，芳烷基，脂族，芳族或环状氨基，膦基，硼基，烷硫基或芳硫基，或烷氧基或芳氧基组; M表示选自Sc，Y，La至Lu的稀土元素，不含ium（Pm）; Q1和Q2独立地表示单阴离子配体; L代表中性路易斯碱。

23. 发明申请

US20100293339A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR VARYING A DATA PREFETCH SIZE BASED UPON DATA USAGE 有权
标题翻译：数据处理系统，用于根据数据使用改变数据预设尺寸的处理器和方法
公开(公告)号：US20100293339A1
公开(公告)日：2010-11-18
申请号：US12024163
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译：一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。基于使用历史来选择由数据预取请求预取的数据量。将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。

24. 发明授权

US07829642B2 Polymerization catalyst composition for polymerization of isoprene compound 失效
标题翻译：用于异戊二烯化合物聚合的聚合催化剂组合物
公开(公告)号：US07829642B2
公开(公告)日：2010-11-09
申请号：US12282148
申请日：2007-02-05
申请人： Zhaomin Hou , Lixin Zhang
发明人： Zhaomin Hou , Lixin Zhang
IPC分类号： C08F36/08 , C08F36/04 , C08F4/44
CPC分类号： C08F36/08 , C08F4/545 , C08F4/52
摘要： 3,4-isoprene-based polymer having high isotacticity can be produced by polymerizing an isoprene compound using a complex represented by the general formula (A) and a catalyst activator: wherein R1 and R2 independently represent an alkyl group, a cyclohexyl group, an aryl group or an aralkyl group; R3 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group, an aralkyl group, an aliphatic, aromatic or cyclic amino group, a phosphino group, a boryl group, an alkylthio or arylthio group, or an alkoxy or aryloxy group; M represents a rare earth element selected from Sc, Y, and La to Lu with promethium (Pm) excluded; Q1 and Q2 independently represent a monoanionic ligand; L represents a neutral Lewis base; and w represents an integer of 0 to 3.
摘要翻译：具有高全同立构规整度的3,4-异戊二烯类聚合物可以通过使用由通式（A）表示的络合物和催化剂活化剂聚合异戊二烯化合物来制备：其中R1和R2独立地表示烷基，环己基，芳基或芳烷基; R3表示烷基，烯基，炔基，芳基，芳烷基，脂族，芳族或环状氨基，膦基，硼基，烷硫基或芳硫基，或烷氧基或芳氧基组; M表示选自Sc，Y，La至Lu的稀土元素，不含ium（Pm）; Q1和Q2独立地表示单阴离子配体; L代表中性路易斯碱; w表示0〜3的整数。

25. 发明授权

US07707396B2 Data processing system, processor and method of data processing having improved branch target address cache 失效
标题翻译：数据处理系统，处理器和数据处理方法具有改进的分支目标地址缓存
公开(公告)号：US07707396B2
公开(公告)日：2010-04-27
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

26. 发明申请

US20090287908A1 PREDICATION SUPPORT IN AN OUT-OF-ORDER PROCESSOR BY SELECTIVELY EXECUTING AMBIGUOUSLY RENAMED WRITE OPERATIONS 有权
标题翻译：通过选择性地执行经过复制的写作操作，在订单处理程序中进行预测支持
公开(公告)号：US20090287908A1
公开(公告)日：2009-11-19
申请号：US12123046
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3005 , G06F9/30072 , G06F9/3842 , G06F9/3885
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译：用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。

27. 发明申请

US20090198982A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE SELECTIVELY APPLYING A DELAYED HIT 有权
标题翻译：数据处理系统，具有分支目标地址高速缓存的数据处理的处理器和方法选择性地应用延迟的HIT
公开(公告)号：US20090198982A1
公开(公告)日：2009-08-06
申请号：US12024190
申请日：2008-02-01
申请人： DAVID S. LEVITAN , Lixin Zhang
发明人： DAVID S. LEVITAN , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3869
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统中取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址预测电路，其存储将第一指令取出地址与要用作第二指令取出地址的分支目标地址相关联的分支目标地址预测。分支目标地址预测电路包括延迟逻辑，响应于与第一指令获取地址匹配的第三指令获取地址的至少一个标签部分，如果没有分支目标地址预测，则使用第二指令获取地址延迟对存储器系统的访问是在上一个操作循环中进行的。

28. 发明申请

US20090198950A1 Techniques for Indirect Data Prefetching 有权
标题翻译：间接数据预取技术
公开(公告)号：US20090198950A1
公开(公告)日：2009-08-06
申请号：US12024239
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译：处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。

29. 发明申请

US20090198910A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA 审中-公开
标题翻译：数据处理系统，处理器和方法，支持部分缓存行数据
公开(公告)号：US20090198910A1
公开(公告)日：2009-08-06
申请号：US12024174
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831
摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that requests a copy of only the target granule for subsequent query access. In response to a combined response to the partial touch request indicating success, the combined response representing a system-wide response to the partial touch request, the processing unit receives the target granule of the target cache line and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于针对包含多个粒子的数据的高速缓存行的目标颗粒的处理器触摸请求，处理单元起源于多处理器数据处理系统的互连部分触摸请求仅请求目标颗粒的副本用于后续查询访问。响应于指示成功的部分触摸请求的组合响应，表示对部分触摸请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒并更新目标颗粒的一致性状态同时保持高速缓存行的至少另一个颗粒的一致性状态。

30. 发明申请

US20070269409A1 Adenoviral Vector Vaccine 有权
标题翻译：腺病毒载体疫苗
公开(公告)号：US20070269409A1
公开(公告)日：2007-11-22
申请号：US10534605
申请日：2003-11-12
申请人： Albert Deisseroth , Lixin Zhang
发明人： Albert Deisseroth , Lixin Zhang
IPC分类号： A61K48/00 , A61K39/00 , C12N15/861
CPC分类号： A61K39/12 , A61K2039/5256 , A61K2039/53 , A61K2039/545 , A61K2039/575 , C07K14/005 , C07K14/70575 , C07K14/70578 , C07K2319/02 , C07K2319/40 , C07K2319/74 , C12N15/86 , C12N2710/10343 , C12N2710/10371 , C12N2710/20022 , C12N2710/20034 , C12N2710/20071
摘要： Provided are adenoviral vectors for generating an immune response to antigen. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal sequence upstream of a tumor antigen upstream of CD40 ligand, which is missing all or substantially all of the transmembrane domain rendering CD40L secretable. Also provided are methods of generating an immune response against cells expressing a tumor antigen by administering an effective amount of the invention vector. Further provided are methods of generating an immune response against cancer expressing a tumor antigen in an individual by administering an effective amount of the invention vector. Still further provided are methods of generating immunity to infection by human papilloma virus (HPV) by administering an effective amount of the invention vector which enocodes the E6 or E7 protein of HPV. The immunity generated is long term.
摘要翻译：提供用于产生对抗原的免疫应答的腺病毒载体。载体包含编码可分泌多肽的转录单元，该多肽包含在CD40配体上游的肿瘤抗原上游的分泌信号序列，其缺失所有或基本上所有的跨膜结构域再现CD40L可分泌。还提供了通过施用有效量的本发明载体产生针对表达肿瘤抗原的细胞的免疫应答的方法。还提供了通过施用有效量的本发明载体产生针对表达个体肿瘤抗原的癌症的免疫应答的方法。还提供了通过施用有效量的本发明的针对HPV的E6或E7蛋白的本发明载体来产生人乳头瘤病毒（HPV）感染免疫的方法。产生的免疫力是长期的。

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