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1. 发明授权

US08266381B2 Varying an amount of data retrieved from memory based upon an instruction hint 失效
标题翻译：根据指令提示改变从存储器检索的数据量
公开(公告)号：US08266381B2
公开(公告)日：2012-09-11
申请号：US12024170
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译：在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

2. 发明申请

US20090198905A1 Techniques for Prediction-Based Indirect Data Prefetching 有权
标题翻译：基于预测的间接数据预取技术
公开(公告)号：US20090198905A1
公开(公告)日：2009-08-06
申请号：US12024248
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/02
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/1027 , G06F2212/6026
摘要： A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.
摘要翻译：使用间接寻址的数据预取技术包括在到存储器的访问流中监视与阵列相关联的数据指针值。该技术确定数据指针值中是否存在模式。然后基于数据指针值中的预测模式，填充与各个阵列地址/数据指针对相对应的条目的预取表。然后，基于预取表中的相应条目，预取（例如，从存储器或另一存储器）分别的数据块（例如，相应的高速缓存行）。

3. 发明申请

US20090198904A1 Techniques for Data Prefetching Using Indirect Addressing with Offset 有权
标题翻译：使用偏移量进行间接寻址的数据预取技术
公开(公告)号：US20090198904A1
公开(公告)日：2009-08-06
申请号：US12024246
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction.
摘要翻译：使用间接寻址执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后取出包含在第一存储器地址的存储器的第一数据块（例如，第一高速缓存行）中的内容。然后将偏移量添加到第一存储器地址处的存储器的内容以提供第一偏移存储器地址。然后基于第一偏移存储器地址确定第二存储器地址。包括第二存储器地址上的数据的第二数据块（例如，第二高速缓存行）然后被取出（例如，从存储器或另一个存储器）。数据预取指令可以由指令中的唯一操作代码（操作码），唯一扩展操作码或字段（包括一个或多个位）来指示。

4. 发明授权

US08250307B2 Sourcing differing amounts of prefetch data in response to data prefetch requests 失效
标题翻译：根据数据预取请求采购不同数量的预取数据
公开(公告)号：US08250307B2
公开(公告)日：2012-08-21
申请号：US12024165
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。预取加载请求指定所请求的数据行。响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。

5. 发明授权

US08166277B2 Data prefetching using indirect addressing 有权
标题翻译：使用间接寻址进行数据预取
公开(公告)号：US08166277B2
公开(公告)日：2012-04-24
申请号：US12024186
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory address. Finally, a data block (e.g., a cache line) including data at the second memory address is fetched (e.g., from the memory or another memory).
摘要翻译：用于执行间接数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后获取第一个存储器地址上的存储器的内容。从第一存储器地址处的存储器的内容确定第二存储器地址。最后，取出包括第二存储器地址上的数据的数据块（例如，高速缓存行）（例如，从存储器或另一个存储器）。

6. 发明授权

US08161265B2 Techniques for multi-level indirect data prefetching 有权
标题翻译：多级间接数据预取技术
公开(公告)号：US08161265B2
公开(公告)日：2012-04-17
申请号：US12024260
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F12/0897 , G06F2212/6026 , G06F2212/681
摘要： A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of a memory) at the first memory address is then fetched. A second memory address is then determined based on the content at the first memory address. Content that is included in a second data block (e.g., a second cache line) at the second memory address is then fetched (e.g., from the memory or another memory). A third memory address is then determined based on the content at the second memory address. Finally, a third data block (e.g., a third cache line) that includes another pointer or data at the third memory address is fetched (e.g., from the memory or the another memory).
摘要翻译：使用多级间接数据预取来执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后取出包含在第一存储器地址的第一数据块（例如，存储器的第一高速缓存行）中的内容。然后基于第一存储器地址处的内容来确定第二存储器地址。包含在第二存储器地址的第二数据块（例如，第二高速缓存行）中的内容然后被取出（例如，从存储器或另一个存储器）。然后基于第二存储器地址处的内容来确定第三存储器地址。最后，取出（例如，从存储器或另一个存储器）中包含第三存储器地址处的另一指针或数据的第三数据块（例如，第三高速缓存行）。

7. 发明授权

US08161263B2 Techniques for indirect data prefetching 有权
标题翻译：间接数据预取技术
公开(公告)号：US08161263B2
公开(公告)日：2012-04-17
申请号：US12024239
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译：处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。

8. 发明申请

US20090198950A1 Techniques for Indirect Data Prefetching 有权
标题翻译：间接数据预取技术
公开(公告)号：US20090198950A1
公开(公告)日：2009-08-06
申请号：US12024239
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译：处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。

9. 发明授权

US08595443B2 Varying a data prefetch size based upon data usage 有权
标题翻译：基于数据使用改变数据预取大小
公开(公告)号：US08595443B2
公开(公告)日：2013-11-26
申请号：US12024163
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译：一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。基于使用历史来选择由数据预取请求预取的数据量。将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。

10. 发明授权

US08209488B2 Techniques for prediction-based indirect data prefetching 有权
标题翻译：基于预测的间接数据预取技术
公开(公告)号：US08209488B2
公开(公告)日：2012-06-26
申请号：US12024248
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/1027 , G06F2212/6026
摘要： A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.
摘要翻译：使用间接寻址的数据预取技术包括在到存储器的访问流中监视与阵列相关联的数据指针值。该技术确定数据指针值中是否存在模式。然后基于数据指针值中的预测模式，填充与各个阵列地址/数据指针对相对应的条目的预取表。然后，基于预取表中的相应条目，预取（例如，从存储器或另一存储器）分别的数据块（例如，相应的高速缓存行）。

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