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21. 发明授权

US09348346B2 Voltage regulation subsystem 有权
标题翻译：电压调节子系统
公开(公告)号：US09348346B2
公开(公告)日：2016-05-24
申请号：US14457129
申请日：2014-08-12
申请人： Kumar Abhishek , Siddi Jai Prakash , Kushal Kamal
发明人： Kumar Abhishek , Siddi Jai Prakash , Kushal Kamal
IPC分类号： G05F1/46
CPC分类号： G05F1/468
摘要： A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.
摘要翻译：微处理器的电压调节子系统具有内部和外部调节模式。选择性地使能内部辅助电压调节器来过载驱动电压。辅助电压调节器的启用取决于在各自调节模式下使用的内部和外部稳压器的带隙基准的比较，其提高了电源电压，使得由外部调节器提供的电路（在辅助电压调节器的辅助下）在极端的过程电压 - 温度（PVT）条件下鲁棒启动。

22. 发明申请

US20150346272A1 SYSTEM FOR TESTING INTEGRATED CIRCUIT 有权
标题翻译：用于测试集成电路的系统
公开(公告)号：US20150346272A1
公开(公告)日：2015-12-03
申请号：US14288358
申请日：2014-05-27
申请人： Kumar Abhishek , Kushal Kamal , Vandana Sapra
发明人： Kumar Abhishek , Kushal Kamal , Vandana Sapra
IPC分类号： G01R31/28
CPC分类号： G01R31/2856 , H03M1/1245 , H03M1/38 , H03M1/40 , H03M1/42 , H03M1/466
摘要： An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.
摘要翻译：集成电路（IC）连接到具有弹簧针的自动测试设备（ATE）。该IC包括模数转换器（ADC），压控振荡器（VCO）和补偿电路。 ATE通过弹簧引脚向ADC提供参考电压信号。在pogo引脚上的电压降引起在ADC产生的数字信号中反映的参考电压信号中的误差。 VCO产生对应于参考电压信号的参考频率信号。补偿电路接收参考频率信号和数字信号，并产生补偿因子信号。补偿电路将补偿因子信号和数字信号相乘以产生补偿数字信号，以补偿由pogo引脚上的电位降引入的误差。

23. 发明授权

US08076979B2 Lock detection circuit for phase locked loop 有权
标题翻译：锁相环锁定检测电路
公开(公告)号：US08076979B2
公开(公告)日：2011-12-13
申请号：US12416933
申请日：2009-04-02
申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
发明人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
IPC分类号： H03J7/04 , H03L7/02
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
摘要翻译：用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器的反馈信号的多个时钟周期。异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。

24. 发明授权

US07952401B2 Standby control circuit and method 有权
标题翻译：待机控制电路和方法
公开(公告)号：US07952401B2
公开(公告)日：2011-05-31
申请号：US12565775
申请日：2009-09-24
申请人： Shankar Ramakrishnan , Kumar Abhishek , Ashish Goel , Ankit Gupta , Chandan Gupta , Mithlesh Shrivas , Rahul Sood
发明人： Shankar Ramakrishnan , Kumar Abhishek , Ashish Goel , Ankit Gupta , Chandan Gupta , Mithlesh Shrivas , Rahul Sood
IPC分类号： H03L7/00
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.
摘要翻译：用于集成电路模块的备用控制电路包括第一控制电路，其在集成电路模块的正常操作模式下响应于指示待机模式输入事件的异步待机信号，以输出与主电源同步的待机模式信号时钟信号以指示集成电路模块的待机操作模式。备用控制电路还包括第二控制电路，其以集成电路模块的降低功率模式响应于指示待机模式输入事件的异步待机信号，以控制第一控制电路输出与指示备用操作模式的辅助时钟信号。

25. 发明申请

US20090251226A1 LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP 有权
标题翻译：锁相环锁定检测电路
公开(公告)号：US20090251226A1
公开(公告)日：2009-10-08
申请号：US12416933
申请日：2009-04-02
申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
发明人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
IPC分类号： H03L7/095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
摘要翻译：用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器的反馈信号的多个时钟周期。异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。

26. 发明申请

US20070255987A1 Control signal synchronization of a scannable storage circuit 有权
标题翻译：可扫描存储电路的控制信号同步
公开(公告)号：US20070255987A1
公开(公告)日：2007-11-01
申请号：US11412532
申请日：2006-04-27
申请人： Kumar Abhishek
发明人： Kumar Abhishek
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/31726
摘要： A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a digital system includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include an input transmission gate to apply any one of a data input and a scan input to a storage element of the storage circuit based on an input circuitry that considers the state of the scan enable signal and a timing signal of a clock associated with the storage element. In addition, a control signal in a master latch of the storage element may synchronously close a hold loop in the master latch when the input transmission gate is opened upon the timing signal of the clock transitioning to a different state.
摘要翻译：公开了一种可扫描存储电路的控制信号同步的方法和/或系统。在一个实施例中，数字系统包括与逻辑电路互连在一起的任何数量的存储电路，以形成功能电路的至少一部分。每个存储电路可以包括输入传输门，用于基于考虑扫描使能信号的状态的输入电路和数据输入和扫描输入的定时信号，将数据输入和扫描输入中的任一个应用于存储电路的存储元件与存储元件相关联的时钟。此外，当时钟转换到不同状态的定时信号打开输入传输门时，存储元件的主锁存器中的控制信号可以同步地闭合主锁存器中的保持环路。

27. 发明授权

US09645195B2 System for testing integrated circuit 有权
公开(公告)号：US09645195B2
公开(公告)日：2017-05-09
申请号：US14288358
申请日：2014-05-27
申请人： Kumar Abhishek , Kushal Kamal , Vandana Sapra
发明人： Kumar Abhishek , Kushal Kamal , Vandana Sapra
IPC分类号： H03M1/12 , G01R31/28 , H03M1/40 , H03M1/42 , H03M1/46 , H03M1/38
CPC分类号： G01R31/2856 , H03M1/1245 , H03M1/38 , H03M1/40 , H03M1/42 , H03M1/466
摘要： An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

28. 发明授权

US09268972B2 Tamper detector power supply with wake-up 有权
标题翻译：篡改检测器电源具有唤醒功能
公开(公告)号：US09268972B2
公开(公告)日：2016-02-23
申请号：US14246132
申请日：2014-04-06
申请人： Siddi Jai Prakash , Kumar Abhishek , Prashant Bhargava , Michael A. Stockinger
发明人： Siddi Jai Prakash , Kumar Abhishek , Prashant Bhargava , Michael A. Stockinger
IPC分类号： G08B21/00 , G06F21/86 , H04Q9/14 , G01D4/00 , G01R22/06
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译：篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。实时时钟（RTC）提供时钟信号并具有电池。处理器由处于供电操作模式的外部电源供电并具有断电模式。在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。特定的I / O端口可以被配置为被动篡改检测。

29. 发明申请

US20150286846A1 TAMPER DETECTOR POWER SUPPLY WITH WAKE-UP 有权
标题翻译：带有唤醒功能的夯实检测器电源
公开(公告)号：US20150286846A1
公开(公告)日：2015-10-08
申请号：US14246132
申请日：2014-04-06
申请人： Siddi Jai Prakash , Kumar Abhishek , Prashant Bhargava , Michael A. Stockinger
发明人： Siddi Jai Prakash , Kumar Abhishek , Prashant Bhargava , Michael A. Stockinger
IPC分类号： G06F21/86 , H04Q9/14 , G01D4/02
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译：篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。实时时钟（RTC）提供时钟信号并具有电池。处理器由处于供电操作模式的外部电源供电并具有断电模式。在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。特定的I / O端口可以被配置为被动篡改检测。

30. 发明授权

US08354879B2 Power switch for decreased ramp rate 有权
标题翻译：降低斜坡率的电源开关
公开(公告)号：US08354879B2
公开(公告)日：2013-01-15
申请号：US13004045
申请日：2011-01-11
申请人： Mukesh Bansal , Kumar Abhishek , Shubhra Singh
发明人： Mukesh Bansal , Kumar Abhishek , Shubhra Singh
IPC分类号： G05F1/10
CPC分类号： H03K17/164
摘要： A power switch for an integrated circuit provides a stepped profile supply potential. A supply potential generation block generates the stepped profile output supply to control the ramp rate of the output in order to prevent a false trigger of electrostatic discharge at the pads of the integrated circuit.
摘要翻译：用于集成电路的电源开关提供阶梯式电源电位。供电电位产生块产生台阶型式输出电源以控制输出的斜坡率，以防止在集成电路的焊盘处的静电放电的错误触发。

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