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21. 发明授权

US06239008B1 Method of making a density multiplier for semiconductor device manufacturing 有权
标题翻译：制造用于半导体器件制造的密度倍增器的方法
公开(公告)号：US06239008B1
公开(公告)日：2001-05-29
申请号：US09407907
申请日：1999-09-29
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L213205
CPC分类号： H01L21/3081 , H01L21/0274 , H01L21/0277 , H01L21/0278 , H01L21/0332
摘要： A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.
摘要翻译：制造具有比制造工艺中使用的光刻系统所提供的尺寸小至少一个尺寸的结构密度增加的半导体器件的方法。

22. 发明授权

US06191036B1 Use of photoresist focus exposure matrix array as via etch monitor 失效
标题翻译：使用光刻胶焦点曝光矩阵阵列作为通孔蚀刻监视器
公开(公告)号：US06191036B1
公开(公告)日：2001-02-20
申请号：US09290354
申请日：1999-04-12
申请人： Allen S. Yu , Paul J. Steffan , Bharath Rangarajan
发明人： Allen S. Yu , Paul J. Steffan , Bharath Rangarajan
IPC分类号： H01L21302
CPC分类号： G03F7/70625 , G03F7/70641 , H01L21/76802 , H01L22/34
摘要： A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.
摘要翻译：在半导体制造工艺中预测通孔的蚀刻效能的方法，其中使用光焦点曝光矩阵（FEM）阵列作为通孔蚀刻监视器。 FEM是矩阵阵列，其中每个阵列具有不同大小的通孔集合。阵列中的矩阵的大小大约是晶片中通孔的最小尺寸的两倍，尺寸减小到最小尺寸的一半左右。

23. 发明授权

US6063685A Device level identification methodology 有权
标题翻译：设备级识别方法
公开(公告)号：US6063685A
公开(公告)日：2000-05-16
申请号：US131284
申请日：1998-08-07
申请人： Paul J. Steffan , Michael McIntyre , Charlie Reading
发明人： Paul J. Steffan , Michael McIntyre , Charlie Reading
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002
摘要： A method of identifying individual semiconductor devices with a unique inscription during the manufacturing process for the semiconductor devices. Each individual semiconductor device is marked during a final lithographic stepping exposure with a direct write laser mounted either in the stepper in the lithographic system working concurrently with the stepping fields during the final metal layer lithographic stepping exposure or during a post stepping pre-development treatment. The marking on the devices includes device identification, lot number and die number.
摘要翻译：一种在半导体器件的制造过程中识别具有独特铭文的各个半导体器件的方法。每个单独的半导体器件在最终光刻步进曝光期间被标记，其中直接写入激光器安装在光刻系统中的步进器中，与最终金属层光刻步进曝光期间或在后期步进预处理中的步进场同时工作。设备上的标记包括设备识别，批号和裸号。

24. 发明授权

US5985753A Method to manufacture dual damascene using a phantom implant mask 有权
标题翻译：使用幻影植入物掩模制造双镶嵌的方法
公开(公告)号：US5985753A
公开(公告)日：1999-11-16
申请号：US136866
申请日：1998-08-19
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/033 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/0337 , H01L21/31144 , H01L21/7681 , H01L21/76813 , H01L2221/1026
摘要： Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.
摘要翻译：制造半导体器件的方法，其中所选择的层以具有要形成在第一层间电介质层中的通孔结构的尺寸的图案中注入重离子。在第一实施例中，将离子注入形成在第一和第二层间电介质层之间的蚀刻停止层中。在第二实施例中，将离子注入第二层间电介质层。选择性蚀刻工艺在第二层间电介质层中形成沟槽结构，并在第一层间电介质层中形成通孔结构。通孔结构和沟槽结构填充有导电材料。

25. 发明授权

US07263451B1 Method and apparatus for correlating semiconductor process data with known prior process data 有权
标题翻译：将半导体工艺数据与已知的先前工艺数据相关联的方法和装置
公开(公告)号：US07263451B1
公开(公告)日：2007-08-28
申请号：US10973181
申请日：2004-10-25
申请人： Jeffrey P. Erhardt , Shivananda S. Shetty , Paul J. Steffan
发明人： Jeffrey P. Erhardt , Shivananda S. Shetty , Paul J. Steffan
IPC分类号： G01N37/00 , G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： A method for correlating semiconductor process data analyzes a semiconductor device that has been treated by a process, to produce process data related to the process. The data is converted into an image pattern, and automatic image retrieval is used to identify other devices having similar images. The process data is then correlated with prior process data of the other devices having the similar images.
摘要翻译：一种使半导体工艺数据相关的方法分析已经被处理过的半导体器件，以产生与该工艺有关的工艺数据。数据被转换为图像图案，并且使用自动图像检索来识别具有相似图像的其他设备。然后将过程数据与具有相似图像的其他设备的先前处理数据相关。

26. 发明授权

US06424881B1 Computer generated recipe selector utilizing defect file information 有权
标题翻译：计算机生成的配方选择器利用缺陷文件信息
公开(公告)号：US06424881B1
公开(公告)日：2002-07-23
申请号：US09404081
申请日：1999-09-23
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of manufacturing semiconductor devices wherein a computer generated list of appropriate review recipes for each layer is available to be used by a review station to review defects on each layer. The most appropriate review recipe is used by the review station unless a review station operator selects an alternate review recipe.
摘要翻译：一种制造半导体器件的方法，其中计算机产生的每个层的适当的审查配方的列表可被审查站用于审查每个层上的缺陷。审查站使用最合适的审查方法，除非审查站操作员选择备用审查配方。

27. 发明授权

US06421574B1 Automatic defect classification system based variable sampling plan 有权
标题翻译：基于自动缺陷分类系统的可变抽样方案
公开(公告)号：US06421574B1
公开(公告)日：2002-07-16
申请号：US09404079
申请日：1999-09-23
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of manufacturing semiconductor devices in which scan data for a current layer of a wafer of a lot being manufactured is compared to previous scan data for previous lots that has been stored in a defect management system. The automatic defect classification system determines whether additional wafers need to be scanned in order to obtain accurate defect data for the production lot to determine whether the current lot should or should not be placed on hold.
摘要翻译：一种制造半导体器件的方法，其中将要制造的批次的晶片的当前层的扫描数据与已经存储在缺陷管理系统中的先前批次的先前扫描数据进行比较。自动缺陷分类系统确定是否需要扫描附加晶片，以获得生产批次的准确缺陷数据，以确定当前批次是否应该被搁置。

28. 发明授权

US06338001B1 In line yield prediction using ADC determined kill ratios die health statistics and die stacking 有权
标题翻译：在线产量预测使用ADC确定的死亡率死亡健康统计和死亡堆叠
公开(公告)号：US06338001B1
公开(公告)日：2002-01-08
申请号：US09255108
申请日：1999-02-22
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of manufacturing and inspecting semiconductor devices wherein defects on inspection wafers are tabulated in a stacked defect table wherein a defect table for each layer is generated per die number and a calculated cumulative die health statistic using an automatic defect classification system and a kill ratio for each defect. The cumulative die health statistic is carried over to the next defect table generated for the next layer.
摘要翻译：一种制造和检查半导体器件的方法，其中检查晶片上的缺陷被列在堆叠缺陷表中，其中使用自动缺陷分类系统生成每层的缺陷表，并且使用自动缺陷分类系统和杀死率每个缺陷。累积的模具健康状况统计量转移到为下一层生成的下一个缺陷表。

29. 发明授权

US06291332B1 Electroless plated semiconductor vias and channels 有权
标题翻译：无电镀半导体通孔和通道
公开(公告)号：US06291332B1
公开(公告)日：2001-09-18
申请号：US09416383
申请日：1999-10-12
申请人： Allen S. Yu , Paul J. Steffan
发明人： Allen S. Yu , Paul J. Steffan
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/288 , H01L21/76879
摘要： A method of manufacturing a semiconductor device is provided in which a semiconductor substrate with a dielectric layer has channel and via openings formed in the dielectric layer. A seed layer is formed over the dielectric layer and in the openings followed by a resist over the seed layer. The resist is then removed outside the openings. The seed layer outside the openings, which is not covered by the resist, is removed and the seed layer in the openings remains intact because of the resist in the openings. The resist inside the openings is removed and the seed layer inside the openings is electroless plated to fill the openings and form the channels and vias for interconnecting the semiconductor device.
摘要翻译：提供了一种制造半导体器件的方法，其中具有介电层的半导体衬底具有形成在电介质层中的沟道和通孔。种子层形成在电介质层之上，并且在开口中形成，随后是种子层上的抗蚀剂。然后将抗蚀剂从开口外部移除。由开口内的抗蚀剂除去未被抗蚀剂覆盖的开口外部的种子层，并且开口中的种子层保持完整。开口内的抗蚀剂被去除，并且开口内的种子层被无电镀以填充开口并形成用于互连半导体器件的通道和通路。

30. 发明授权

US06287922B1 Method for fabricating graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极型材制造分级LDD晶体管的方法
公开(公告)号：US06287922B1
公开(公告)日：2001-09-11
申请号：US09162426
申请日：1998-09-28
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L21/28114 , H01L21/823814 , H01L21/82385 , H01L29/665 , H01L29/66545 , H01L29/6659 , Y10S438/978
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles.
摘要翻译：通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层，在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有倾斜轮廓的侧壁，以及用掺杂剂注入所述半导体衬底以穿透所述侧壁的部分以形成具有逐渐掺杂分布的一个或多个渐变浅结。

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