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21. 发明授权

US07570078B1 Programmable logic device providing serial peripheral interfaces 有权
标题翻译：提供串行外设接口的可编程逻辑器件
公开(公告)号：US07570078B1
公开(公告)日：2009-08-04
申请号：US11761221
申请日：2007-06-11
申请人： Howard Tang , Roger Spinti , San-Ta Kow
发明人： Howard Tang , Roger Spinti , San-Ta Kow
IPC分类号： H03K19/177 , G11C8/00
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17748 , H03K19/17756
摘要： Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). In one example, a method of operating a PLD includes receiving a configuration data bitstream at a slave serial peripheral interface (SPI) port of a PLD from a master SPI port of a first external device. The method also includes passing the configuration data bitstream through the PLD from the slave SPI port of the PLD to a master SPI port of the PLD. The method further includes providing the configuration data bitstream from the master SPI port of the PLD to a slave SPI port of a second external device.
摘要翻译：本文公开了系统和方法，以提供诸如可编程逻辑器件（PLD）之类的集成电路的配置的改进方法。在一个示例中，操作PLD的方法包括从第一外部设备的主SPI端口接收PLD的从串行外设接口（SPI）端口的配置数据比特流。该方法还包括将配置数据比特流通过PLD从PLD的从SPI端口传递到PLD的主SPI端口。该方法还包括将配置数据比特流从PLD的主SPI端口提供给第二外部设备的从SPI端口。

22. 发明申请

US20050189962A1 Upgradeable and reconfigurable programmable logic device 有权
标题翻译：可升级和可重新配置的可编程逻辑器件
公开(公告)号：US20050189962A1
公开(公告)日：2005-09-01
申请号：US10783886
申请日：2004-02-20
申请人： Om Agrawal , Howard Tang , Jack Wong
发明人： Om Agrawal , Howard Tang , Jack Wong
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17732 , H03K19/1776 , H03K19/17768
摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.
摘要翻译：公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。例如，根据本发明的实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

23. 发明授权

US5658442A Target and dark space shield for a physical vapor deposition system 失效
标题翻译：用于物理气相沉积系统的靶和暗空间屏蔽
公开(公告)号：US5658442A
公开(公告)日：1997-08-19
申请号：US612053
申请日：1996-03-07
申请人： James Van Gogh , Fernand Dorleans , Christopher Hagerty , Mark Lloyd , Howard Tang , Siyaun Yang , R. Steve West
发明人： James Van Gogh , Fernand Dorleans , Christopher Hagerty , Mark Lloyd , Howard Tang , Siyaun Yang , R. Steve West
IPC分类号： C23C14/34 , H01J37/34
CPC分类号： H01J37/3441 , C23C14/3407 , H01J37/3408 , H01J37/3423 , H01J37/3447
摘要： The disadvantages heretofore associated with the prior art are overcome by the present invention of an improved target for a physical deposition (PVD) system. The improved target has a portion of the target side wall the overhangs and shadows the side wall of the target thus preventing material from depositing on the edge. To further reduce contaminant generation, the improved target is combined with an improved dark space shield having a first end and a second end, where the second end conventionally supports a collimator and the first end has an inner surface that is substantially vertical.
摘要翻译：迄今与现有技术相关的缺点由本发明克服了用于物理沉积（PVD）系统的改进目标。改进的目标具有目标侧壁的一部分突出并且影响目标的侧壁，从而防止材料沉积在边缘上。为了进一步减少污染物产生，改进的目标与具有第一端和第二端的改进的暗空间屏蔽结合，其中第二端通常支撑准直器，并且第一端具有基本垂直的内表面。

24. 发明授权

US08584959B2 Power-on sequencing for an RFID tag 有权
标题翻译： RFID标签的上电顺序
公开(公告)号：US08584959B2
公开(公告)日：2013-11-19
申请号：US13490115
申请日：2012-06-06
申请人： Agustin Ochoa , Howard Tang
发明人： Agustin Ochoa , Howard Tang
IPC分类号： G06K19/06
CPC分类号： G06K19/0715 , G06K19/0712
摘要： Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.
摘要翻译：用于铁电RFID电路的排序电路包括用于接收外部电压的输入节点，耦合到输入节点的带隙电路，耦合到带隙电路的带隙就绪电路，具有耦合到输入节点的输入端和带隙就绪电路，耦合到所述转换滤波器的输出的滤波电容器以及LDO调节器，其具有耦合到所述转换滤波器的输出的输入端，所述输入端具有用于存储器部分中的多个调节电压，数字电路部分和用于产生复位信号。排序电路还包括用于在操作模式之间引入受控延迟的延迟电路，用于监视电源电压的POR单元和用于监视内部节点以控制关闭脉冲发生器的数字状态机。

25. 发明申请

US20120313592A1 SHUNT REGULATOR CIRCUIT HAVING A SPLIT OUTPUT 有权
标题翻译：具有分路输出的分路调节器电路
公开(公告)号：US20120313592A1
公开(公告)日：2012-12-13
申请号：US13490296
申请日：2012-06-06
申请人： Agustin Ochoa , Howard Tang
发明人： Agustin Ochoa , Howard Tang
IPC分类号： G05F1/613
CPC分类号： G05F1/613 , G06K19/0715
摘要： A shunt regulator for an RFID tag chip is powered from split outputs from the RF rectifier, including a first output for providing a power delivery path to on-chip circuits and a second output for providing a discharge-regulation path. The shunt regulator includes a capacitor coupled between the first output and ground. The shunt regulator further includes an input node for receiving a power supply voltage from the rectifier split outputs, a first diode having an anode coupled to the input node, a second diode having an anode coupled to the input node, a resistor divider circuit and amplifier coupled between a cathode of the first diode and ground, transistor having a control terminal coupled to an output of the resistor divider and amplifier circuit, and a current path coupled between a cathode of the second diode and ground.
摘要翻译：用于RFID标签芯片的分流调节器由来自RF整流器的分离输出供电，包括用于提供片上电路的功率输送路径的第一输出和用于提供放电调节路径的第二输出。并联调节器包括耦合在第一输出和地之间的电容器。分流调节器还包括输入节点，用于从整流器分流输出端接收电源电压，第一二极管具有耦合到输入节点的阳极，具有耦合到输入节点的阳极的第二二极管，电阻分压器电路和放大器耦合在第一二极管的阴极和地之间，具有耦合到电阻分压器和放大器电路的输出的控制端的晶体管和耦合在第二二极管的阴极和地之间的电流通路。

26. 发明授权

US07737723B1 Transparent field reconfiguration for programmable logic devices 有权
标题翻译：可编程逻辑器件的透明场重新配置
公开(公告)号：US07737723B1
公开(公告)日：2010-06-15
申请号：US12467800
申请日：2009-05-18
申请人： Howard Tang , Jack T. Wong , Clark Wilkinson , Jeffrey S. Byrne
发明人： Howard Tang , Jack T. Wong , Clark Wilkinson , Jeffrey S. Byrne
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17744 , H03K19/1776
摘要： In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.
摘要翻译：根据本发明的实施例，可编程逻辑器件（PLD，诸如现场可编程门阵列（FPGA））包括多个输入/输出块，其适于在可编程逻辑器件中预处理寄存器，其具有期望的信号值将输入/输出块的控制释放到由重新配置提供的用户定义的逻辑。

27. 发明授权

US07725803B1 Programmable logic device programming verification systems and methods 有权
标题翻译：可编程逻辑器件编程验证系统和方法
公开(公告)号：US07725803B1
公开(公告)日：2010-05-25
申请号：US11557808
申请日：2006-11-08
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
IPC分类号： H03M13/00 , G01R31/28
CPC分类号： H03K19/1776 , H03K19/17764 , H03M13/09
摘要： In accordance with an embodiment of the present invention, a programmable logic device includes configuration memory to store configuration data to configure the programmable logic device, and a non-volatile memory to store configuration data for transfer to the configuration memory to configure the programmable logic device. The non-volatile memory also stores a first code value based on the configuration data stored in the non-volatile memory. A code block calculates a second code value based on the configuration data transferred to the configuration memory. A comparator compares the first code value to the second code value to verify that the configuration data was not corrupted during the transfer from the non-volatile memory to the configuration memory.
摘要翻译：根据本发明的实施例，可编程逻辑器件包括用于存储配置数据以配置可编程逻辑器件的配置存储器和用于存储用于传送到配置存储器的配置数据以配置可编程逻辑器件的非易失性存储器。非易失性存储器还存储基于存储在非易失性存储器中的配置数据的第一代码值。代码块基于传送到配置存储器的配置数据来计算第二代码值。比较器将第一代码值与第二代码值进行比较，以验证在从非易失性存储器传输到配置存储器期间配置数据未被破坏。

28. 发明授权

US07631223B1 Programmable logic device methods and system for providing multi-boot configuration data support 有权
标题翻译：可编程逻辑器件方法和系统，用于提供多引导配置数据支持
公开(公告)号：US07631223B1
公开(公告)日：2009-12-08
申请号：US11447591
申请日：2006-06-06
申请人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
发明人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , H03K19/17764 , H03K19/17772
摘要： Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.
摘要翻译：本文公开了各种技术以提供将配置数据加载到可编程逻辑器件的配置存储器中的改进方法。例如，根据本发明的一个实施例，配置可编程逻辑器件的方法包括从外部存储器件的第一存储器块读取第一位流。检查第一比特流的错误，并且如果检测到错误，则从外部存储器装置的第二存储器块读取第二比特流。可编程逻辑器件的配置存储器被编程为在第一比特流和第二比特流之一中提供的配置数据。

29. 发明授权

US07554358B1 Programmable logic devices with user non-volatile memory 有权
标题翻译：具有用户非易失性存储器的可编程逻辑器件
公开(公告)号：US07554358B1
公开(公告)日：2009-06-30
申请号：US11397985
申请日：2006-04-05
申请人： Fabiano Fontana , Henry Law , Howard Tang , Om P. Agrawal , David L. Rutledge
发明人： Fabiano Fontana , Henry Law , Howard Tang , Om P. Agrawal , David L. Rutledge
IPC分类号： H01L25/00
CPC分类号： H03K19/17772 , H03K19/1776
摘要： Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.
摘要翻译：本文公开了系统和方法，以提供用于可编程逻辑器件的改进的非易失性存储技术。例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块，多个输入/输出块和用于在可编程逻辑器件内存储数据的易失性存储器，配置存储器适于存储用于配置逻辑块，输入/输出块和可编程逻辑器件的易失性存储器的第一配置数据。可编程逻辑器件还包括适于存储从易失性存储器提供的数据的非易失性存储器。

30. 发明授权

US07535253B1 Register data retention systems and methods during reprogramming of programmable logic devices 有权
标题翻译：在可编程逻辑器件重新编程期间注册数据保留系统和方法
公开(公告)号：US07535253B1
公开(公告)日：2009-05-19
申请号：US11941006
申请日：2007-11-15
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ju Shen
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ju Shen
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/1776
摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.
摘要翻译：根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。例如，根据实施例，一种方法包括在可编程逻辑和可编程逻辑器件的寄存器之间编程路由资源，以在重新编程之前提供用于数据的数据路径; 在重新编程之前，通过数据路径将数据从可编程逻辑转移到寄存器，以便在重新编程期间将数据存储在可编程逻辑器件内; 重新编程可编程逻辑器件，其中重新编程在可编程逻辑器件和可编程逻辑器件的寄存器之间提供重新编程的数据通路; 并且在可编程逻辑器件的重新编程已经完成之后，通过可编程逻辑器件从寄存器传送数据以供可编程逻辑使用。

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