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1. 发明授权

US08060784B1 Programmable logic device and methods for providing multi-boot configuration data support 有权
标题翻译：可编程逻辑器件和方法，用于提供多引导配置数据支持
公开(公告)号：US08060784B1
公开(公告)日：2011-11-15
申请号：US12630163
申请日：2009-12-03
申请人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
发明人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , H03K19/17764 , H03K19/17772
摘要： In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件包括配置存储器和控制器。控制器可以从非易失性存储器的第一存储器块读取第一比特流，并且检测第一比特流是否包含有效前同步码，因为第一比特流是从非易失性存储器读取的，并且在第一比特流中的配置数据被编程为易失性配置存储器。如果在第一比特流中检测到有效的前导码，则控制器使用第一比特流中的配置数据来对配置存储器进行编程。如果在第一比特流中没有检测到有效的前导码，则控制器从非易失性存储器的第二存储器块读取第二比特流。

2. 发明授权

US07725803B1 Programmable logic device programming verification systems and methods 有权
标题翻译：可编程逻辑器件编程验证系统和方法
公开(公告)号：US07725803B1
公开(公告)日：2010-05-25
申请号：US11557808
申请日：2006-11-08
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
IPC分类号： H03M13/00 , G01R31/28
CPC分类号： H03K19/1776 , H03K19/17764 , H03M13/09
摘要： In accordance with an embodiment of the present invention, a programmable logic device includes configuration memory to store configuration data to configure the programmable logic device, and a non-volatile memory to store configuration data for transfer to the configuration memory to configure the programmable logic device. The non-volatile memory also stores a first code value based on the configuration data stored in the non-volatile memory. A code block calculates a second code value based on the configuration data transferred to the configuration memory. A comparator compares the first code value to the second code value to verify that the configuration data was not corrupted during the transfer from the non-volatile memory to the configuration memory.
摘要翻译：根据本发明的实施例，可编程逻辑器件包括用于存储配置数据以配置可编程逻辑器件的配置存储器和用于存储用于传送到配置存储器的配置数据以配置可编程逻辑器件的非易失性存储器。非易失性存储器还存储基于存储在非易失性存储器中的配置数据的第一代码值。代码块基于传送到配置存储器的配置数据来计算第二代码值。比较器将第一代码值与第二代码值进行比较，以验证在从非易失性存储器传输到配置存储器期间配置数据未被破坏。

3. 发明授权

US07631223B1 Programmable logic device methods and system for providing multi-boot configuration data support 有权
标题翻译：可编程逻辑器件方法和系统，用于提供多引导配置数据支持
公开(公告)号：US07631223B1
公开(公告)日：2009-12-08
申请号：US11447591
申请日：2006-06-06
申请人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
发明人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , H03K19/17764 , H03K19/17772
摘要： Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.
摘要翻译：本文公开了各种技术以提供将配置数据加载到可编程逻辑器件的配置存储器中的改进方法。例如，根据本发明的一个实施例，配置可编程逻辑器件的方法包括从外部存储器件的第一存储器块读取第一位流。检查第一比特流的错误，并且如果检测到错误，则从外部存储器装置的第二存储器块读取第二比特流。可编程逻辑器件的配置存储器被编程为在第一比特流和第二比特流之一中提供的配置数据。

4. 发明授权

US08108754B1 Programmable logic device programming verification systems and methods 有权
标题翻译：可编程逻辑器件编程验证系统和方法
公开(公告)号：US08108754B1
公开(公告)日：2012-01-31
申请号：US12786359
申请日：2010-05-24
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
IPC分类号： H03M13/00 , G01R31/28
CPC分类号： H03K19/1776 , H03K19/17764 , H03M13/09
摘要： In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.
摘要翻译：在一个实施例中，验证可编程逻辑器件的编程操作的方法包括在可编程逻辑器件配置数据内的非易失性存储器中存储和基于配置数据的预先计算的代码值。该方法还包括将配置数据从非易失性存储器转移到可编程逻辑器件内的配置存储器; 基于从所述非易失性存储器传送到所述配置存储器的配置数据计算代码值; 以及将计算的代码值与预先计算的代码值进行比较。

5. 发明授权

US07768300B1 Programmable logic device providing serial peripheral interfaces 有权
标题翻译：提供串行外设接口的可编程逻辑器件
公开(公告)号：US07768300B1
公开(公告)日：2010-08-03
申请号：US12511388
申请日：2009-07-29
申请人： Howard Tang , Roger Spinti , San-Ta Kow
发明人： Howard Tang , Roger Spinti , San-Ta Kow
IPC分类号： H03K19/177 , G11C8/00
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17748 , H03K19/17756
摘要： In one embodiment, a programmable logic device (PLD) includes a slave port and a master port. The slave port can receive a configuration data bitstream and a slave clock signal from a master port of a first external device. The master port can provide the configuration data bitstream and a master clock signal from the PLD to a slave port of a second external device. An interface block in the PLD can pass the configuration data bitstream from the slave port through the PLD to the master port. In another embodiment, a PLD includes a slave serial peripheral interface (SPI) port and configuration memory. The slave SPI port can receive a configuration data bitstream and a slave clock signal from a master SPI port of an external device. The configuration memory stores the received bitstream for configuring the PLD.
摘要翻译：在一个实施例中，可编程逻辑器件（PLD）包括从端口和主端口。从端口可以从第一外部设备的主端口接收配置数据比特流和从时钟信号。主端口可以将配置数据比特流和来自PLD的主时钟信号提供给第二外部设备的从端口。 PLD中的接口块可以将配置数据比特流从从端口通过PLD传递到主端口。在另一个实施例中，PLD包括从串行外设接口（SPI）端口和配置存储器。从站SPI端口可以从外部设备的主SPI端口接收配置数据位流和从时钟信号。配置存储器存储用于配置PLD的接收比特流。

6. 发明授权

US07876125B1 Register data retention systems and methods during reprogramming of programmable logic devices 有权
标题翻译：在可编程逻辑器件重新编程期间注册数据保留系统和方法
公开(公告)号：US07876125B1
公开(公告)日：2011-01-25
申请号：US12464822
申请日：2009-05-12
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ju Shen
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ju Shen
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/1776
摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.
摘要翻译：根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。例如，在一个实施例中，可编程逻辑器件包括适于在可编程逻辑器件的操作期间生成用户数据的多个逻辑块; 多个寄存器，适于在可编程逻辑器件的重新编程操作期间存储用户数据; 以及适于在逻辑块和寄存器之间提供编程数据路径的可配置路由资源。

7. 发明授权

US07535253B1 Register data retention systems and methods during reprogramming of programmable logic devices 有权
标题翻译：在可编程逻辑器件重新编程期间注册数据保留系统和方法
公开(公告)号：US07535253B1
公开(公告)日：2009-05-19
申请号：US11941006
申请日：2007-11-15
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ju Shen
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ju Shen
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/1776
摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.
摘要翻译：根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。例如，根据实施例，一种方法包括在可编程逻辑和可编程逻辑器件的寄存器之间编程路由资源，以在重新编程之前提供用于数据的数据路径; 在重新编程之前，通过数据路径将数据从可编程逻辑转移到寄存器，以便在重新编程期间将数据存储在可编程逻辑器件内; 重新编程可编程逻辑器件，其中重新编程在可编程逻辑器件和可编程逻辑器件的寄存器之间提供重新编程的数据通路; 并且在可编程逻辑器件的重新编程已经完成之后，通过可编程逻辑器件从寄存器传送数据以供可编程逻辑使用。

8. 发明授权

US07570078B1 Programmable logic device providing serial peripheral interfaces 有权
标题翻译：提供串行外设接口的可编程逻辑器件
公开(公告)号：US07570078B1
公开(公告)日：2009-08-04
申请号：US11761221
申请日：2007-06-11
申请人： Howard Tang , Roger Spinti , San-Ta Kow
发明人： Howard Tang , Roger Spinti , San-Ta Kow
IPC分类号： H03K19/177 , G11C8/00
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17748 , H03K19/17756
摘要： Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). In one example, a method of operating a PLD includes receiving a configuration data bitstream at a slave serial peripheral interface (SPI) port of a PLD from a master SPI port of a first external device. The method also includes passing the configuration data bitstream through the PLD from the slave SPI port of the PLD to a master SPI port of the PLD. The method further includes providing the configuration data bitstream from the master SPI port of the PLD to a slave SPI port of a second external device.
摘要翻译：本文公开了系统和方法，以提供诸如可编程逻辑器件（PLD）之类的集成电路的配置的改进方法。在一个示例中，操作PLD的方法包括从第一外部设备的主SPI端口接收PLD的从串行外设接口（SPI）端口的配置数据比特流。该方法还包括将配置数据比特流通过PLD从PLD的从SPI端口传递到PLD的主SPI端口。该方法还包括将配置数据比特流从PLD的主SPI端口提供给第二外部设备的从SPI端口。

9. 发明授权

US08069329B1 Internally triggered reconfiguration of programmable logic devices 有权
标题翻译：可编程逻辑器件的内部触发重新配置
公开(公告)号：US08069329B1
公开(公告)日：2011-11-29
申请号：US12021202
申请日：2008-01-28
申请人： Howard Tang , Roger Spinti , Jeff Byrne , Clark Wilkinson
发明人： Howard Tang , Roger Spinti , Jeff Byrne , Clark Wilkinson
IPC分类号： G06F12/00
CPC分类号： H03K19/17752 , G06F17/5054 , H03K19/17756 , H03K19/1776
摘要： Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also includes a bus interface adapted to interface with configuration data storage memory. The PLD further includes user logic configured by the first configuration data and adapted to provide a reconfiguration signal to trigger a reconfiguration of the PLD. In addition, the PLD includes a bus interface controller responsive to the reconfiguration signal for loading second configuration data from the configuration data storage memory via the bus interface.
摘要翻译：描述了各种技术来提供可编程逻辑器件（PLD）的内部触发的重新配置。在一个示例中，PLD包括适于存储第一配置数据以配置PLD用于其预期功能的配置存储器。 PLD还包括适于与配置数据存储存储器连接的总线接口。 PLD还包括由第一配置数据配置的用户逻辑，并且适于提供重配置信号以触发PLD的重新配置。此外，PLD包括响应于重新配置信号的总线接口控制器，用于经由总线接口从配置数据存储存储器加载第二配置数据。

10. 发明授权

US08384427B1 Configuring multiple programmable logic devices with serial peripheral interfaces 有权
标题翻译：使用串行外设接口配置多个可编程逻辑器件
公开(公告)号：US08384427B1
公开(公告)日：2013-02-26
申请号：US12752455
申请日：2010-04-01
申请人： Howard Tang , Roger Spinti
发明人： Howard Tang , Roger Spinti
IPC分类号： H03K19/177 , G11C8/00
CPC分类号： H03K19/1776
摘要： In one embodiment, a programmable logic device includes configuration memory, an SPI port for receiving a bitstream, a chip select output pin, and configuration control circuitry. The chip select output pin can provide a chip select signal having a first logic state for selecting another device (such as another PLD) to receive a bitstream and a second logic state for de-selecting the other device. The configuration control circuitry is responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state, thereby selecting the other device to receive the bitstream. Several such PLDs connected in a daisy chain can thus be configured from a single configuration source or have their configuration data read back while so connected.
摘要翻译：在一个实施例中，可编程逻辑器件包括配置存储器，用于接收比特流的SPI端口，芯片选择输出引脚和配置控制电路。芯片选择输出引脚可以提供具有第一逻辑状态的芯片选择信号，用于选择另一个设备（例如另一个PLD）以接收比特流，以及用于取消选择另一个设备的第二逻辑状态。配置控制电路响应嵌入在所接收的比特流中的命令，以将芯片选择输出引脚从第二逻辑状态驱动到第一逻辑状态，从而选择另一个设备来接收比特流。因此，以菊花链方式连接的几个这样的PLD可以由单个配置源配置，或者在连接时将其配置数据读回。

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