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1. 发明授权

US08108754B1 Programmable logic device programming verification systems and methods 有权
标题翻译：可编程逻辑器件编程验证系统和方法
公开(公告)号：US08108754B1
公开(公告)日：2012-01-31
申请号：US12786359
申请日：2010-05-24
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
IPC分类号： H03M13/00 , G01R31/28
CPC分类号： H03K19/1776 , H03K19/17764 , H03M13/09
摘要： In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.
摘要翻译：在一个实施例中，验证可编程逻辑器件的编程操作的方法包括在可编程逻辑器件配置数据内的非易失性存储器中存储和基于配置数据的预先计算的代码值。该方法还包括将配置数据从非易失性存储器转移到可编程逻辑器件内的配置存储器; 基于从所述非易失性存储器传送到所述配置存储器的配置数据计算代码值; 以及将计算的代码值与预先计算的代码值进行比较。

2. 发明授权

US07725803B1 Programmable logic device programming verification systems and methods 有权
标题翻译：可编程逻辑器件编程验证系统和方法
公开(公告)号：US07725803B1
公开(公告)日：2010-05-25
申请号：US11557808
申请日：2006-11-08
申请人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
发明人： Howard Tang , Roger Spinti , San-Ta Kow , Ann Wu
IPC分类号： H03M13/00 , G01R31/28
CPC分类号： H03K19/1776 , H03K19/17764 , H03M13/09
摘要： In accordance with an embodiment of the present invention, a programmable logic device includes configuration memory to store configuration data to configure the programmable logic device, and a non-volatile memory to store configuration data for transfer to the configuration memory to configure the programmable logic device. The non-volatile memory also stores a first code value based on the configuration data stored in the non-volatile memory. A code block calculates a second code value based on the configuration data transferred to the configuration memory. A comparator compares the first code value to the second code value to verify that the configuration data was not corrupted during the transfer from the non-volatile memory to the configuration memory.
摘要翻译：根据本发明的实施例，可编程逻辑器件包括用于存储配置数据以配置可编程逻辑器件的配置存储器和用于存储用于传送到配置存储器的配置数据以配置可编程逻辑器件的非易失性存储器。非易失性存储器还存储基于存储在非易失性存储器中的配置数据的第一代码值。代码块基于传送到配置存储器的配置数据来计算第二代码值。比较器将第一代码值与第二代码值进行比较，以验证在从非易失性存储器传输到配置存储器期间配置数据未被破坏。

3. 发明授权

US07631223B1 Programmable logic device methods and system for providing multi-boot configuration data support 有权
标题翻译：可编程逻辑器件方法和系统，用于提供多引导配置数据支持
公开(公告)号：US07631223B1
公开(公告)日：2009-12-08
申请号：US11447591
申请日：2006-06-06
申请人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
发明人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , H03K19/17764 , H03K19/17772
摘要： Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.
摘要翻译：本文公开了各种技术以提供将配置数据加载到可编程逻辑器件的配置存储器中的改进方法。例如，根据本发明的一个实施例，配置可编程逻辑器件的方法包括从外部存储器件的第一存储器块读取第一位流。检查第一比特流的错误，并且如果检测到错误，则从外部存储器装置的第二存储器块读取第二比特流。可编程逻辑器件的配置存储器被编程为在第一比特流和第二比特流之一中提供的配置数据。

4. 发明授权

US08060784B1 Programmable logic device and methods for providing multi-boot configuration data support 有权
标题翻译：可编程逻辑器件和方法，用于提供多引导配置数据支持
公开(公告)号：US08060784B1
公开(公告)日：2011-11-15
申请号：US12630163
申请日：2009-12-03
申请人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
发明人： Roger Spinti , Howard Tang , San-Ta Kow , Ann Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , H03K19/17764 , H03K19/17772
摘要： In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件包括配置存储器和控制器。控制器可以从非易失性存储器的第一存储器块读取第一比特流，并且检测第一比特流是否包含有效前同步码，因为第一比特流是从非易失性存储器读取的，并且在第一比特流中的配置数据被编程为易失性配置存储器。如果在第一比特流中检测到有效的前导码，则控制器使用第一比特流中的配置数据来对配置存储器进行编程。如果在第一比特流中没有检测到有效的前导码，则控制器从非易失性存储器的第二存储器块读取第二比特流。

5. 发明授权

US07589648B1 Data decompression 有权
标题翻译：数据解压缩
公开(公告)号：US07589648B1
公开(公告)日：2009-09-15
申请号：US11054855
申请日：2005-02-10
申请人： Benny Ma , San-Ta Kow , Ann Wu , Thomas Tsui
发明人： Benny Ma , San-Ta Kow , Ann Wu , Thomas Tsui
IPC分类号： H03M7/00
CPC分类号： H03M7/3086 , Y10S707/99942
摘要： In one embodiment, a data decompression circuit for a data stream having a repeated data word is provided. The data stream is compressed into a series of data frames such that the repeated data word is removed from the series of data frames and such that each data frame corresponds to a header. The circuit includes a decompression engine configured to decompress each data frame into a corresponding decompressed data frame, the decompression engine being further configured to decode each header to identify whether word locations in the corresponding decompressed data frame should be filled with the repeated data word.
摘要翻译：在一个实施例中，提供了具有重复数据字的数据流的数据解压缩电路。数据流被压缩成一系列数据帧，使得重复的数据字从一系列数据帧中移除，并且使得每个数据帧对应于报头。该电路包括解压缩引擎，其被配置为将每个数据帧解压缩为对应的解压缩数据帧，所述解压缩引擎还被配置为对每个报头进行解码以识别对应的解压缩数据帧中的字位置是否应填充有重复的数据字。

6. 发明授权

US07902865B1 Compression and decompression of configuration data using repeated data frames 有权
标题翻译：使用重复数据帧对配置数据进行压缩和解压缩
公开(公告)号：US07902865B1
公开(公告)日：2011-03-08
申请号：US11941031
申请日：2007-11-15
申请人： Chan-Chi Jason Cheng , San-Ta Kow , Ann Wu
发明人： Chan-Chi Jason Cheng , San-Ta Kow , Ann Wu
IPC分类号： H01L25/00 , H03M5/00 , G06F17/50
CPC分类号： G06F17/5054 , H03M7/30
摘要： Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also includes embedding a first instruction to instruct a PLD to load the first data frame into a data shift register, embedding a second instruction to instruct the PLD to load a first address associated with the first data frame into an address shift register, and embedding a third instruction to instruct the PLD to load the first data frame from the data shift register into a first row of a configuration memory corresponding to the first address. The method further includes identifying a second data frame comprising the data set in the uncompressed bitstream, and embedding fourth and fifth instructions in place of the second data frame.
摘要翻译：提供了各种技术来压缩和解压缩与可编程逻辑器件（PLD）一起使用的配置数据。在一个示例中，一种方法包括将包括来自未压缩比特流的数据集的第一数据帧嵌入到压缩比特流中。该方法还包括嵌入第一指令以指示PLD将第一数据帧加载到数据移位寄存器中，嵌入第二指令以指示PLD将与第一数据帧相关联的第一地址加载到地址移位寄存器中，以及嵌入第三指令以指示PLD将第一数据帧从数据移位寄存器加载到与第一地址对应的配置存储器的第一行中。该方法还包括识别包括未压缩比特流中的数据集的第二数据帧，以及代替第二数据帧嵌入第四和第五指令。

7. 发明授权

US07596744B1 Auto recovery from volatile soft error upsets (SEUs) 有权
标题翻译：从易失性软错误（SEU）自动恢复
公开(公告)号：US07596744B1
公开(公告)日：2009-09-29
申请号：US11361584
申请日：2006-02-24
申请人： San-Ta Kow , Ann Wu , Tou Nou Thao
发明人： San-Ta Kow , Ann Wu , Tou Nou Thao
IPC分类号： G06F7/02 , G01R31/28
CPC分类号： H03K19/17752 , G06F11/1004 , H03K19/17756 , H03K19/17764
摘要： In one embodiment, a programmable logic device for recovery from soft error upsets (SEUs) includes: a configuration memory operable to store configuration data; a configuration engine operable to configure the configuration memory; an error detection circuit operable to determine if the stored configuration data in the configuration memory has an error; and a configuration reset circuit operable to trigger the configuration engine to reconfigure the configuration memory if the error detection circuit detects the error.
摘要翻译：在一个实施例中，用于从软错误异常（SEU）恢复的可编程逻辑器件包括：可操作以存储配置数据的配置存储器; 配置引擎，用于配置所述配置存储器; 错误检测电路，用于确定配置存储器中存储的配置数据是否具有错误; 以及配置复位电路，其可操作以在所述错误检测电路检测到所述错误时触发所述配置引擎重配置所述配置存储器。

8. 发明授权

US08058898B1 Compression and decompression of configuration data using repeated data frames 有权
标题翻译：使用重复数据帧对配置数据进行压缩和解压缩
公开(公告)号：US08058898B1
公开(公告)日：2011-11-15
申请号：US13034174
申请日：2011-02-24
申请人： Chan-Chi Jason Cheng , San-Ta Kow , Ann Wu
发明人： Chan-Chi Jason Cheng , San-Ta Kow , Ann Wu
IPC分类号： H03K19/173 , H03M5/00 , G06F17/50
CPC分类号： G06F17/5054 , H03M7/30
摘要： In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherein the first data frame comprises a first data set; embedding a first instruction into the compressed bitstream to load the first data frame into a first row of configuration memory of the PLD at an address associated with the first data frame; identifying a second data frame in the uncompressed bitstream, wherein the second data frame comprises the first data set; and embedding a second instruction into the compressed bitstream to load the first data frame into a second row of the configuration memory at an address associated with the second data frame.
摘要翻译：在一个实施例中，公开了一种将未压缩比特流转换为用于可编程逻辑器件（PLD）的压缩比特流的方法。该方法包括将来自未压缩比特流的第一数据帧嵌入到压缩比特流中，其中第一数据帧包括第一数据集; 将第一指令嵌入到所述压缩比特流中，以将所述第一数据帧加载到与所述第一数据帧相关联的地址的所述PLD的第一行配置存储器中; 识别所述未压缩比特流中的第二数据帧，其中所述第二数据帧包括所述第一数据集; 以及将第二指令嵌入所述压缩比特流中，以与所述第二数据帧相关联的地址将所述第一数据帧加载到所述配置存储器的第二行。

9. 发明授权

US08010871B1 Auto recovery from volatile soft error upsets (SEUs) 有权
标题翻译：从易失性软错误（SEU）自动恢复
公开(公告)号：US08010871B1
公开(公告)日：2011-08-30
申请号：US12561140
申请日：2009-09-16
申请人： San-Ta Kow , Ann Wu , Tou Nou Thao
发明人： San-Ta Kow , Ann Wu , Tou Nou Thao
IPC分类号： H03M13/00
CPC分类号： H03K19/17752 , G06F11/1004 , H03K19/17756 , H03K19/17764
摘要： A method of recovering from a soft error within configuration data stored in a configured programmable logic device. The method includes repeatedly processing the configuration data stored within configuration memory of the device using an error-detection algorithm to generate a checksum. The generated checksum is compared with a previously generated checksum to detect if a soft error exists in the configuration data. If a soft error is detected, the programmable logic device initiates a reconfiguration of the configuration memory. The configuration memory is then reconfigured with the configuration data while preventing the programmable logic device from responding to the reconfiguration as though the reconfiguration was an initial configuration of the device. An embodiment of a programmable logic device designed for practicing the method is also disclosed.
摘要翻译：从存储在配置的可编程逻辑器件中的配置数据内的软错误中恢复的方法。该方法包括使用错误检测算法重复处理存储在设备的配置存储器内的配置数据，以生成校验和。将生成的校验和与先前生成的校验和进行比较，以检测配置数据中是否存在软错误。如果检测到软错误，则可编程逻辑器件启动配置存储器的重新配置。然后，配置存储器被配置数据重新配置，同时防止可编程逻辑器件响应重新配置，就好像重新配置是设备的初始配置一样。还公开了设计用于实施该方法的可编程逻辑器件的实施例。

10. 发明授权

US07088132B1 Configuring FPGAs and the like using one or more serial memory devices 有权
标题翻译：使用一个或多个串行存储设备配置FPGA等
公开(公告)号：US07088132B1
公开(公告)日：2006-08-08
申请号：US11243255
申请日：2005-10-04
申请人： Howard Tang , Satwant Singh , Ann Wu
发明人： Howard Tang , Satwant Singh , Ann Wu
IPC分类号： H03K19/177
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17748
摘要： The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration data stored in the memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the FPGA. In one embodiment, the FPGA has an Serial Peripheral Interface (SPI) that is connected to the SPI interface of each of one or more SPI serial flash PROMs operating as boot PROMs. When there are two or more boot PROMs, each PROM stores a portion of the FPGA's configuration data and the FPGA interleaves the data from multiple boot PROMs to generate a serial configuration data bitstream. The present invention enables boot PROMs having different sizes and/or storing different amounts of configuration data to be simultaneously connected to an FPGA to support efficient configuration architectures.
摘要翻译：用于可编程器件（例如FPGA）的配置架构包括直接连接到FPGA的一个或多个存储器件，使得FPGA可配置存储在存储器件中的配置数据，而不通过连接在任何的存储器件和FPGA。在一个实施例中，FPGA具有串行外设接口（SPI），其连接到作为引导PROM操作的一个或多个SPI串行闪存PROM中的每一个的SPI接口。当存在两个或更多个引导PROM时，每个PROM存储FPGA配置数据的一部分，并且FPGA交互来自多个引导PROM的数据以生成串行配置数据比特流。本发明使得具有不同尺寸和/或存储不同数量的配置数据的引导PROM能够同时连接到FPGA以支持有效的配置架构。

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