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21. 发明授权

US06489233B2 Non-metallic barrier formations for copper damascene type interconnects 有权
标题翻译：铜镶嵌型互连的非金属阻挡层
公开(公告)号：US06489233B2
公开(公告)日：2002-12-03
申请号：US09925821
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
摘要翻译：用于形成具有非金属屏障的双镶嵌型导电互连的方法，其保护所述互连免受氟周围的低k，氟化介电材料的氟扩散。该方法的一个实施例特别适用于在0.15微米级的微电子制造中形成这种互连。

22. 发明授权

US06465888B2 Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene 有权
标题翻译：复合硅 - 金属氮化物屏障，以防铜铜镶嵌中金属氟化物的形成
公开(公告)号：US06465888B2
公开(公告)日：2002-10-15
申请号：US10043604
申请日：2002-01-14
申请人： Simon Chooi , Subhash Gupta , Mei Sheng Zhou , Sang Ki Hong
发明人： Simon Chooi , Subhash Gupta , Mei Sheng Zhou , Sang Ki Hong
IPC分类号： H01L2352
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L21/76855
摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure—single, dual, or multi-structure—is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.
摘要翻译：公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止铜中氟化物的形成。在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连双镶嵌结构的墙壁。在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构底部蚀刻钝化/阻挡层，形成底层铜层。在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。

23. 发明授权

US06436824B1 Low dielectric constant materials for copper damascene 有权
标题翻译：用于铜镶嵌的低介电常数材料
公开(公告)号：US06436824B1
公开(公告)日：2002-08-20
申请号：US09346526
申请日：1999-07-02
申请人： Simon Chooi , Mei Sheng Zhou , Yi Xu
发明人： Simon Chooi , Mei Sheng Zhou , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/02211 , H01L21/02167 , H01L21/02274 , H01L21/3125 , H01L21/314 , H01L21/76807
摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.
摘要翻译：提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。

24. 发明授权

US06376353B1 Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects 有权
标题翻译：用于铜镶嵌互连的铝和铜双金属焊盘方案
公开(公告)号：US06376353B1
公开(公告)日：2002-04-23
申请号：US09609167
申请日：2000-07-03
申请人： Mei Sheng Zhou , Sangki Hong , Simon Chooi
发明人： Mei Sheng Zhou , Sangki Hong , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/32134 , H01L21/76807 , H01L21/7684 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2224/48824 , H01L2924/00 , H01L2924/00015 , H01L2924/013 , H01L2924/00013
摘要： Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al—Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al—Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al—Cu bond layer or region is placed on top of the underlying copper pad metal. This Al—Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.
摘要翻译：本发明公开了用于在纯铜镶嵌件上制造引线接合焊盘的改进方法。本发明涉及用于半导体集成电路器件的各种制造方法，更具体地涉及形成Al-Cu合金顶部焊盘金属层，其改善了引线接合，顶部Al-Cu和下面的铜焊盘之间的粘附冶金。本发明描述了其中特殊的Al-Cu键合层或区域放置在下面的铜垫金属的顶部上的工艺。纯铜上的这种Al-Cu键合焊盘（其间具有阻挡层）提供了改善的与焊盘焊接粘合的线粘合，并且防止了焊线粘附试验期间的剥离。

25. 发明授权

US06372636B1 Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene 有权
标题翻译：复合硅 - 金属氮化物屏障，以防铜铜镶嵌中金属氟化物的形成
公开(公告)号：US06372636B1
公开(公告)日：2002-04-16
申请号：US09587467
申请日：2000-06-05
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L21/76855
摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.
摘要翻译：公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止在铜中形成氟化物。在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连双镶嵌结构的墙壁。在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构的底部蚀刻钝化/阻挡层，形成底层铜层。在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。

26. 发明授权

US06368958B2 Method to deposit a cooper seed layer for dual damascence interconnects 失效
标题翻译：沉积铜离子种子层用于双重马氏体互连的方法
公开(公告)号：US06368958B2
公开(公告)日：2002-04-09
申请号：US09876598
申请日：2001-06-08
申请人： Paul Kwok Keung Ho , Subhash Gupta , Mei Sheng Zhou , Simon Chooi
发明人： Paul Kwok Keung Ho , Subhash Gupta , Mei Sheng Zhou , Simon Chooi
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , C23C18/1608 , C25D7/123 , H01L21/288 , H01L21/76873 , H01L21/76874 , H01L21/76877
摘要： A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer. The copper layer may comprise a thin seed layer for use in subsequent electroplating or electroless plating of copper or may comprise a thick copper layer to fill the vias and trenches. The integrated circuit is completed.
摘要翻译：已经实现了在制造集成电路器件中使用Cu（I）离子从由极性有机溶剂稳定的溶液中进行歧化的单层和双镶嵌互连的沉积铜层的新方法。提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。图案化电介质层以形成用于计划的双镶嵌互连的通孔和沟槽。沉积覆盖在介电层上的阻挡层以对通孔和沟槽进行排列。将由极性有机溶剂稳定的简单的Cu（I）离子溶液涂覆在所述阻挡层上。向稳定化的简单的Cu（I）离子溶液中加入水以引起Cu（I）离子溶液中简单的Cu（I）离子的歧化。沉积在屏障层上的铜层。铜层可以包括用于铜的后续电镀或无电镀的薄种子层，或者可以包括用于填充通孔和沟槽的厚铜层。集成电路完成。

27. 发明授权

US06340608B1 Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads 失效
标题翻译：在端接铜焊盘上制造用于倒装芯片或芯片上IC封装的铜金属凸块的方法
公开(公告)号：US06340608B1
公开(公告)日：2002-01-22
申请号：US09612564
申请日：2000-07-07
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho , Xu Yi
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho , Xu Yi
IPC分类号： H01L2150
CPC分类号： H01L24/81 , H01L2224/13147 , H01L2224/81801 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.
摘要翻译：提供了具有暴露的金属端接垫的半导体芯片，以及具有其上相应的暴露的金属轨道的单独的基板。在暴露的金属端接垫上方形成金属凸块。在金属凸块上形成感光树脂插头。半导体芯片的金属凸块与分离的基板上的对应金属轨迹对准。金属凸块上的感光树脂插头与相应的金属轨道配合。感光树脂插头暴露于紫外线光以固化光敏树脂插头，将半导体芯片的金属凸块永久地连接到单独基板的相应金属轨道上。

28. 发明授权

US06271115B1 Post metal etch photoresist strip method 失效
标题翻译：后金属蚀刻光刻胶剥离法
公开(公告)号：US06271115B1
公开(公告)日：2001-08-07
申请号：US09604065
申请日：2000-06-26
申请人： Wen Jun Liu , Simon Chooi , Mei Sheng Zhou , Raymond Joy
发明人： Wen Jun Liu , Simon Chooi , Mei Sheng Zhou , Raymond Joy
IPC分类号： H01L214763
CPC分类号： H01L21/02071
摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O2 and H2O; the second step is in a microwave generated plasma containing O2 and N2; the third step is in a microwave generated plasma containing H2O; the fourth step is in a microwave generated plasma containing O2 and N2; and the fifth step is in a microwave generated plasma containing H2O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.
摘要翻译：已经开发了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。该方法是五步法，其中第一步是在微波产生的含有O 2和H 2 O的等离子体中; 第二步是在微波产生的含有O2和N2的等离子体中; 第三步是在微波产生的含有H 2 O的等离子体中; 第四步是在微波产生的含有O2和N2的等离子体中; 并且第五步是在含有H 2 O的微波产生的等离子体中。在同时开始钝化过程的同时开始除去光致抗蚀剂的第一步骤在蚀刻含氯蚀刻剂中的铝或铝 - 铜层之后会导致残留物去除光致抗蚀剂。

29. 发明授权

US06261942B1 Dual metal-oxide layer as air bridge 有权
标题翻译：双金属氧化物层作为气桥
公开(公告)号：US06261942B1
公开(公告)日：2001-07-17
申请号：US09490156
申请日：2000-01-24
申请人： Mei Sheng Zhou , Simon Chooi , Xu Yi
发明人： Mei Sheng Zhou , Simon Chooi , Xu Yi
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , H01L21/312 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.
摘要翻译：一种在微电子制造中将空气引入相邻导电结构之间的间隙中以减少它们之间的电容耦合的方法。图案化的金属层沉积在基底上。该层衬有CVD氧化物。一次性间隙填充材料沉积在衬里的金属层上。通过在CVD氧化物层上沉积TiN层，在间隙填充上形成两层“空气桥”。这种结构通过几种化学方法使其多孔化。氧气等离子体通过多孔空气桥与其下方的间隙填充反应并溶解。反应产物通过多孔气桥逸出，导致空气填充的间隙。

30. 发明授权

US5948701A Self-aligned contact (SAC) etching using polymer-building chemistry 失效
标题翻译：使用聚合物构建化学的自对准接触（SAC）蚀刻
公开(公告)号：US5948701A
公开(公告)日：1999-09-07
申请号：US902846
申请日：1997-07-30
申请人： Simon Chooi , Mei-Sheng Zhou , Jian Xun Li
发明人： Simon Chooi , Mei-Sheng Zhou , Jian Xun Li
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/3065
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76804
摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures. The first plasma etch method employs an etchant gas composition which forms a passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then formed upon the third dielectric layer a patterned photoresist layer which defines the location between the pair of structures to be formed the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then etched through the first plasma etch method the third dielectric layer and the second conformal dielectric layer to form a partial via while forming the passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first dielectric layer. Finally, there is then etched through a second plasma etch method the first conformal dielectric layer to form the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer.
摘要翻译：在微电子学制造中通过介电层形成通孔的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成一对微电子结构。然后在包括一对微电子结构的基板上依次形成第一共形介电层，随后是第二共形介电层，随后是第三介电层，其中第二共形绝缘层用作相对于第三绝缘层的蚀刻停止层在第一等离子体蚀刻方法中使用的介电层，其用于在所述一对微电子结构之间的位置处部分地通过所述第三介电层，所述第二共形介电层和所述第一共形介电层形成通孔。第一等离子体蚀刻方法采用蚀刻剂气体组合物，其在第三介电层，第二共形介电层和第一共形介电层的非水平部分上形成钝化氟碳聚合物层。然后在第三电介质层上形成图案化的光致抗蚀剂层，该图案化的光致抗蚀剂层限定通过第三介电层，第二共形介电层和第一共形介电层形成通孔的一对结构之间的位置。然后通过第一等离子体蚀刻方法蚀刻第三介电层和第二共形介电层以形成部分通孔，同时在第三介电层，第二共形介电层和第二保形介电层的非水平部分上形成钝化氟碳聚合物层第一电介质层。最后，然后通过第二等离子体蚀刻方法蚀刻第一共形介电层，以通过第三介电层，第二共形介电层和第一共形介电层形成通孔。

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