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21. 发明申请

US20090108869A1 Design Structure for a Flexible Multimode Logic Element For Use In A Configurable Mixed-Logic Signal Distribution Path 失效
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构
公开(公告)号：US20090108869A1
公开(公告)日：2009-04-30
申请号：US11931626
申请日：2007-10-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/00
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

22. 发明申请

US20090022203A1 METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT 有权
标题翻译：集成电路供电方法与系统
公开(公告)号：US20090022203A1
公开(公告)日：2009-01-22
申请号：US11780530
申请日：2007-07-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G01J5/00
CPC分类号： G05D23/20 , G05D23/1934
摘要： Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

23. 发明授权

US07479819B2 Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees 失效
公开(公告)号：US07479819B2
公开(公告)日：2009-01-20
申请号：US11610848
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

24. 发明授权

US07429877B2 Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构
公开(公告)号：US07429877B2
公开(公告)日：2008-09-30
申请号：US11848470
申请日：2007-08-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，用于示例性多模电路的设计结构可以被配置为以全摆动模式，限定摆动模式，全摆幅至限定摆动转换器模式和限定摆动转换模式中的一种运行，摆动转换器模式。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

25. 发明授权

US07378890B2 Programmable low-power high-frequency divider 有权
公开(公告)号：US07378890B2
公开(公告)日：2008-05-27
申请号：US11857632
申请日：2007-09-19
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

26. 发明授权

US07075350B2 Programmable low-power high-frequency divider 失效
公开(公告)号：US07075350B2
公开(公告)日：2006-07-11
申请号：US11070730
申请日：2005-03-02
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/356
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

27. 发明授权

US07049864B2 Apparatus and method for high frequency state machine divider with low power consumption 失效
标题翻译：具有低功耗的高频状态机分频器的装置和方法
公开(公告)号：US07049864B2
公开(公告)日：2006-05-23
申请号：US10710115
申请日：2004-06-18
申请人： Ram Kelkar , Pradeep Thiagarajan
发明人： Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00
CPC分类号： G06F1/04 , G06F1/025
摘要： A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
摘要翻译：数字分频装置包括多个下一状态发生器元件，其接收输入时钟信号，并且被配置为为相应的多个内部状态变量中的每一个生成下一个值。多个触发器元件被配置为存储针对多个内部状态变量的所生成的下一个值，所述多个触发器元件还被配置为向下一个状态发生器提供多个内部状态变量的当前值元件通过它们之间的反馈路径。所生成的多个内部状态变量的下一个值基于多个内部状态变量和输入时钟信号的当前值。

28. 发明申请

US20050280449A1 APPARATUS AND METHOD FOR HIGH FREQUENCY STATE MACHINE DIVIDER WITH LOW POWER CONSUMPTION 失效
标题翻译：低功耗高频状态机分路器的装置和方法
公开(公告)号：US20050280449A1
公开(公告)日：2005-12-22
申请号：US10710115
申请日：2004-06-18
申请人： Ram Kelkar , Pradeep Thiagarajan
发明人： Ram Kelkar , Pradeep Thiagarajan
IPC分类号： G06F1/025 , G06F1/04 , H03K21/00
CPC分类号： G06F1/04 , G06F1/025
摘要： A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
摘要翻译：数字分频装置包括多个下一状态发生器元件，其接收输入时钟信号，并且被配置为为相应的多个内部状态变量中的每一个生成下一个值。多个触发器元件被配置为存储针对多个内部状态变量的所生成的下一个值，所述多个触发器元件还被配置为向下一个状态发生器提供多个内部状态变量的当前值元件通过它们之间的反馈路径。所生成的多个内部状态变量的下一个值基于多个内部状态变量和输入时钟信号的当前值。

29. 发明申请

US20130120041A1 Leakage Tolerant Delay Locked Loop Circuit Device 有权
标题翻译：泄漏容限延迟锁定环路电路装置
公开(公告)号：US20130120041A1
公开(公告)日：2013-05-16
申请号：US13295351
申请日：2011-11-14
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0816
摘要： Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.
摘要翻译：提供了泄漏容限延迟锁定环（DLL）电路装置以及使用泄漏容限DLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括DLL电路装置，包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器和压控缓冲器（VCB）。二次校正电路被配置为产生并向误差控制器提供二次误差延迟信号。二次校正电路包括多个误差发生器。响应于检测到来自VCB的输出相位信号的特定边缘，每个误差发生器被配置为产生二次误差延迟信号。主回路被配置为基于第一误差延迟增加信号，第一误差延迟降低信号和次级误差延迟信号中的至少一个来控制相位调整。

30. 发明授权

US08302037B2 Skewed double differential pair circuit for offset cancellation 有权
标题翻译：偏移双差分对电路
公开(公告)号：US08302037B2
公开(公告)日：2012-10-30
申请号：US12494642
申请日：2009-06-30
申请人： Igor Arsovski , Anthony R Bonaccio , Hayden (Clay) Cranford, Jr. , Joseph A Iadanza , Pradeep Thiagarajan , Sebastian T Ventrone , Benjamin T Voegeli
发明人： Igor Arsovski , Anthony R Bonaccio , Hayden (Clay) Cranford, Jr. , Joseph A Iadanza , Pradeep Thiagarajan , Sebastian T Ventrone , Benjamin T Voegeli
IPC分类号： G06F17/50
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.
摘要翻译：公开了一种使用双差分输入对系统产生具有偏移消除的差分信号的差分系统。它使用两个有意偏斜的并联差分晶体管对。名义上，差分对在每个方向相反的方向上倾斜，但是具有相等的幅度，使得两个差分对的组合被名义上平衡。然后，使用用于在系统的校准模式中为第一和第二差分输入提供等电位值的选择装置，增加或减少通过每个差分对的电流，直到任何偏移被充分抵消为止，以及用于比较第一和第第二差分输出在校准模式下确定系统的偏移。

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