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21. 发明授权

US06643179B2 Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell 有权
公开(公告)号：US06643179B2
公开(公告)日：2003-11-04
申请号：US10047918
申请日：2002-01-14
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1600
CPC分类号： G11C11/5621 , G11C7/067 , G11C11/56 , G11C11/5642 , G11C11/565 , G11C16/26
摘要： The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

22. 发明授权

US06515911B2 Circuit structure for providing a hierarchical decoding in semiconductor memory devices 失效
标题翻译：用于在半导体存储器件中提供分层解码的电路结构
公开(公告)号：US06515911B2
公开(公告)日：2003-02-04
申请号：US09894975
申请日：2001-06-27
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1606
CPC分类号： G11C16/0416 , G11C8/14
摘要： A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common is presented. The device includes a PMOS first transistor having conduction terminals connected respectively to the main word line and the local word line, an NMOS second transistor having conduction terminals connected respectively to the local word line and the main word line, and a PMOS third transistor having conduction terminals connected respectively to the main word line and the local word line. Such a third transistor is a charge transistor that reduces the charging time for the local word line.
摘要翻译：一种电路装置，其被构造为能够实现非易失性类型的半导体存储器件中的行解码的分层形式，并且包括具有被组织成列的扇区的存储器单元的矩阵，其中每个扇区具有单独连接到主体的一组本地字线提供了通过具有共同行的所有矩阵扇区的字线。该器件包括具有分别连接到主字线和本地字线的导通端子的PMOS第一晶体管，具有分别连接到本地字线和主字线的导通端子的NMOS第二晶体管和具有导通的PMOS第三晶体管端子分别连接到主字线和本地字线。这样的第三晶体管是减少本地字线的充电时间的电荷晶体管。

23. 发明授权

US06456530B1 Nonvolatile memory device with hierarchical sector decoding 有权
标题翻译：具有分层扇区解码的非易失性存储器件
公开(公告)号：US06456530B1
公开(公告)日：2002-09-24
申请号：US09602680
申请日：2000-06-26
申请人： Rino Micheloni , Matteo Zammattio , Giovanni Campardo
发明人： Rino Micheloni , Matteo Zammattio , Giovanni Campardo
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C16/12
摘要： The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.
摘要翻译：存储器件具有分级扇区解码。提供多组供应管线，每个扇区行一个平行于扇区行延伸。多个开关级各自连接在相应的扇区和相应的一组供电线之间; 连接到布置在同一列上的扇区的开关级由与扇区列平行延伸的控制线上提供的相同控制信号控制。为了偏置扇区，修改电压被发送到至少一组选定的偏置线，并且控制信号被发送到连接到所选扇区列的切换级。

24. 发明授权

US6094073A Line decoder for memory devices 有权
标题翻译：用于存储器件的线路解码器
公开(公告)号：US6094073A
公开(公告)日：2000-07-25
申请号：US432642
申请日：1999-11-02
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C8/10 , G11C16/12 , H03K19/082
CPC分类号： G11C8/10 , G11C16/12
摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
摘要翻译：行解码器包括提供有行地址并产生预解码信号的预解码级; 以及最终解码阶段，其基于预解码信号驱动阵列中的各行。预解码阶段包括多个预解码电路，其呈现两个并行信号路径：在读取模式中使用的低电压路径，以及在编程模式中使用的高压路径。 CMOS开关将两路径分开，通过编程模式下的电压转换器由高电压驱动，并且在预解码级别形成，不涉及集成问题。

25. 发明授权

US6075750A Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权
标题翻译：用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译：一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。

26. 发明授权

US5886925A Read circuit and method for nonvolatile memory cells with an equalizing structure 失效
标题翻译：具有均衡结构的非易失性存储单元的读取电路和方法
公开(公告)号：US5886925A
公开(公告)日：1999-03-23
申请号：US877922
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
摘要翻译：读取电路提供电流镜电路，其包括插入在电源线和相应的第一和第二输出节点之间的第一和第二负载晶体管。第一输出节点连接到要读取的单元，第二输出节点连接到产生具有预定特性的参考电流的发生级，并且第二负载晶体管的尺寸大于第一负载晶体管的N倍。为了即使在低电源电压并且没有初始不确定性的情况下也允许快速电池读取，均衡电路提供连接在第一输出节点和地之间的电流平衡支路，用于产生与参考值1 / N的比率的均衡电流电流在开始读数之前平衡电路。

27. 发明授权

US06947329B2 Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices 有权
标题翻译：用于检测非易失性存储器电子设备中的电阻路径或预定电位的方法
公开(公告)号：US06947329B2
公开(公告)日：2005-09-20
申请号：US10675805
申请日：2003-09-30
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C8/02 , G11C29/00 , G11C29/02 , G11C16/04
CPC分类号： G11C29/82 , G11C29/02 , G11C29/025 , G11C29/50008 , G11C29/83 , G11C29/832
摘要： The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.
摘要翻译：本发明涉及一种用于精确定位擦除故障存储器单元的方法和可编程和电可擦除类型的相关集成非易失性存储器件，其包括以行和列布置的存储器单元的分区阵列，具有至少一个行 - 每个扇区的解码电路部分被提供正和负电压。该方法在负擦除算法问题上变得可操作，并且包括以下步骤：强制尚未被完全擦除的扇区的读取条件; 扫描所述扇区的行以检查是否存在指示故障状态的杂散电流; 发现故障行并将其电隔离以将其重新寻址到在同一扇区中提供的冗余行。

28. 发明授权

US06871258B2 METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE 失效
标题翻译：用于擦除电可擦除非易失性存储器件的方法，特别是EEPROM闪速存储器件，以及特别是EEPROM闪速存储器件的电可擦除非易失性存储器件
公开(公告)号：US06871258B2
公开(公告)日：2005-03-22
申请号：US10159780
申请日：2002-05-30
申请人： Rino Micheloni , Giovanni Campardo , Salvatrice Scommegna
发明人： Rino Micheloni , Giovanni Campardo , Salvatrice Scommegna
IPC分类号： G11C16/34 , G06F12/00
CPC分类号： G11C16/344 , G11C16/3436
摘要： Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.
摘要翻译：这里描述了一种用于电可擦除非易失性存储器件，特别是EEPROM闪存非易失性存储器件的擦除方法，其特征在于包括由排列成行和列的多个存储单元形成的存储器阵列，子行业，其又由一行或多行形成。存储器阵列的擦除由扇区执行，并且对于每个扇区，设想对扇区的所有存储器单元的栅极端子施加擦除脉冲，验证每个子部件的存储器单元的擦除，以及向栅极施加另外的擦除脉冲只有子部分的存储器单元的端子不被完全擦除。

29. 发明授权

US06724658B2 Method and circuit for generating reference voltages for reading a multilevel memory cell 有权
标题翻译：用于产生用于读取多级存储单元的参考电压的方法和电路
公开(公告)号：US06724658B2
公开(公告)日：2004-04-20
申请号：US10133231
申请日：2002-04-26
申请人： Rino Micheloni , Giovanni Campardo
发明人： Rino Micheloni , Giovanni Campardo
IPC分类号： G11C1600
CPC分类号： G11C11/5621 , G11C5/147 , G11C7/067 , G11C11/56 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5634
摘要： The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.
摘要翻译：用于产生用于读取多电平存储器单元的参考电压的电路包括：分别具有第一参考编程电平和第二参考编程电平的第一存储单元和第二存储单元; 分别连接到所述第一和所述第二存储单元的第一参考电路和第二参考电路，并具有分别提供第一参考电压和第二参考电压的相应输出端; 以及分压器，具有分别连接到第一参考电路和第二参考电路的输出端的第一连接节点和第二连接节点，以分别接收第一参考电压和第二参考电压，以及多个中间节点以相等的距离提供相应的第三参考电压。

30. 发明授权

US06532171B2 Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units 有权
标题翻译：能够选择性地擦除多个元件存储器单元的非易失性半导体存储器
公开(公告)号：US06532171B2
公开(公告)日：2003-03-11
申请号：US09919789
申请日：2001-07-31
申请人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
发明人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1616
CPC分类号： G11C16/3431 , G11C16/16 , G11C16/34
摘要： A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.
摘要翻译：诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列形成包。具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

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