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21. 发明申请

US20060215435A1 METHOD FOR REDUCING A RESET CURRENT FOR RESETTING A PORTION OF A PHASE CHANGE MATERIAL IN A MEMORY CELL OF A PHASE CHANGE MEMORY DEVICE AND THE PHASE CHANGE MEMORY DEVICE 有权
标题翻译：一种复位电流的方法，用于复位相变存储器件和相变存储器件的存储器单元中的相变材料的部分
公开(公告)号：US20060215435A1
公开(公告)日：2006-09-28
申请号：US11420933
申请日：2006-05-30
申请人： Chang-Wook JEONG , Jun-Hyok Kong , Ji-Hye Yi , Beak-Hyung Cho
发明人： Chang-Wook JEONG , Jun-Hyok Kong , Ji-Hye Yi , Beak-Hyung Cho
IPC分类号： G11C11/42
CPC分类号： G11C13/0004 , G11C2013/0083 , Y10S977/754
摘要： According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example the first crystalline phase may be a hexagonal closed packed structure and the first crystalline phase may be a face centered cubic structure.
摘要翻译：根据一个实施方案，包括第一结晶相的至少一部分相变材料转化为第二结晶相和非晶相之一。第二结晶相比第一结晶相更容易转变成非晶态。例如，第一结晶相可以是六方密封填充结构，第一结晶相可以是面心立方结构。

22. 发明申请

US20060072370A1 Phase-changeable memory devices and methods of forming the same 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20060072370A1
公开(公告)日：2006-04-06
申请号：US11205742
申请日：2005-08-17
申请人： Bong-Jin Kuh , Yong-Ho Ha , Ji-Hye Yi
发明人： Bong-Jin Kuh , Yong-Ho Ha , Ji-Hye Yi
IPC分类号： G11C8/02
CPC分类号： G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , Y10S438/90
摘要： A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. A nitride layer may be formed on the insulating interlayer. The lower electrode may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the lower electrode. Methods of forming phase-changeable memory devices are also disclosed.
摘要翻译：相变型存储器件包括在其上表面具有接触区域的衬底。衬底上的绝缘中间层具有开口，并且在开口中形成下电极。下电极具有氮化表面部分并且与衬底的接触区域电接触。相变材料层图案位于下电极上，上电极位于相变材料层图案上。绝缘中间层可以具有氮化表面部分，并且相变材料层可以至少部分地在绝缘中间层的氮化表面部分上。可以在绝缘中间层上形成氮化物层。下部电极可以具有氮化表面部分，并且相变材料层可以至少部分地位于下部电极的氮化表面部分上。还公开了形成相变存储器件的方法。

23. 发明授权

US06686240B2 Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same 失效
标题翻译：具有多重隧道结层图案的半导体存储器件及其制造方法
公开(公告)号：US06686240B2
公开(公告)日：2004-02-03
申请号：US10394030
申请日：2003-03-24
申请人： Ji-Hye Yi , Woo-Sik Kim
发明人： Ji-Hye Yi , Woo-Sik Kim
IPC分类号： H01L218242
CPC分类号： H01L21/28273 , H01L21/32134 , H01L27/11521 , H01L29/42324 , H01L29/7881 , H01L29/88
摘要： A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.
摘要翻译：一种半导体存储器件及其制造方法，其中半导体存储器件包括在半导体衬底，存储节点和多个隧道结层图案的预定区域处并行形成的第一和第二导电区域，以及第二导电区域，堆叠在所述多个隧道结层图案上的数据线，以及覆盖所述存储节点和所述多重隧道结层图案的两个侧壁的字线，其中所述存储节点的两个侧壁具有用于增加所述重叠的底切区域存储节点的区域和字线。存储节点通过交替地且重复地堆叠具有不同蚀刻速率的第一和第二导电层，连续地图案化导电层以形成存储节点图案，并且选择性地和各向同性地蚀刻存储节点图案的第一或第二导电层。

24. 发明授权

US08338261B2 Semiconductor device including field effect transistor and method of forming the same 有权
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US08338261B2
公开(公告)日：2012-12-25
申请号：US12851965
申请日：2010-08-06
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

25. 发明授权

US07889548B2 Method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and the phase change memory device 有权
标题翻译：减少用于复位相变存储器件和相变存储器件的存储单元中的相变材料的一部分的复位电流的方法
公开(公告)号：US07889548B2
公开(公告)日：2011-02-15
申请号：US12585637
申请日：2009-09-21
申请人： Chang-Wook Jeong , Jun-Hyok Kong , Ji-Hye Yi , Beak-Hyung Cho
发明人： Chang-Wook Jeong , Jun-Hyok Kong , Ji-Hye Yi , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2013/0083 , Y10S977/754
摘要： According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.
摘要翻译：根据一个实施方案，包括第一结晶相的至少一部分相变材料转化为第二结晶相和非晶相之一。第二结晶相比第一结晶相更容易转变成非晶态。例如，第一结晶相可以是六方密封填充结构，并且第一结晶相可以是面心立方结构。

26. 发明授权

US07879668B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07879668B2
公开(公告)日：2011-02-01
申请号：US12343134
申请日：2008-12-23
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.
摘要翻译：在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。在基板和第一和第二栅电极上形成具有第一应力的层。掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。在凹部中形成具有第二应力的图案。

27. 发明申请

US20100221879A1 Methods of Manufacturing Phase-Changeable Memory Devices 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US20100221879A1
公开(公告)日：2010-09-02
申请号：US12777599
申请日：2010-05-11
申请人： Bong-Jin Kuh , Yong-Ho Ha , Ji-Hye Yi
发明人： Bong-Jin Kuh , Yong-Ho Ha , Ji-Hye Yi
IPC分类号： H01L21/8239 , H01L45/00
CPC分类号： G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , Y10S438/90
摘要： A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. Methods of forming phase-changeable memory devices are also disclosed.
摘要翻译：相变型存储器件包括在其上表面具有接触区域的衬底。衬底上的绝缘中间层具有开口，并且在开口中形成下电极。下电极具有氮化表面部分并且与衬底的接触区域电接触。相变材料层图案位于下电极上，上电极位于相变材料层图案上。绝缘中间层可以具有氮化表面部分，并且相变材料层可以至少部分地在绝缘中间层的氮化表面部分上。还公开了形成相变存储器件的方法。

28. 发明授权

US07482616B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US07482616B2
公开(公告)日：2009-01-27
申请号：US11139283
申请日：2005-05-27
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L29/02
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

29. 发明申请

US20080067609A1 Semiconductor Device Including Field Effct Transistor and Method of Forming the Same 有权
标题翻译：包括场效应晶体管的半导体器件及其形成方法
公开(公告)号：US20080067609A1
公开(公告)日：2008-03-20
申请号：US11857157
申请日：2007-09-18
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

30. 发明申请

US20050002227A1 Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same 有权
标题翻译：包括氮和/或硅的相变存储器件及其制造方法
公开(公告)号：US20050002227A1
公开(公告)日：2005-01-06
申请号：US10910945
申请日：2004-08-04
申请人： Horii Hideki , Bong-Jin Kuh , Yong-Ho Ha , Jeong-hee Park , Ji-Hye Yi
发明人： Horii Hideki , Bong-Jin Kuh , Yong-Ho Ha , Jeong-hee Park , Ji-Hye Yi
IPC分类号： G11C16/02 , H01L27/24 , H01L45/00 , G11C11/00
CPC分类号： H01L45/143 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystalline structure.
摘要翻译：提供了可相变存储器件和制造可相变存储器件的方法，其包括可包括氮原子和/或硅原子的相变材料的相变材料图案。第一和第二电极电连接到相变材料图案并向其提供电信号。相变材料图案可以具有多晶结构。

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