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21. 发明申请

US20100237466A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20100237466A1
公开(公告)日：2010-09-23
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L29/92
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

22. 发明申请

US20100099248A1 Methods of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20100099248A1
公开(公告)日：2010-04-22
申请号：US12588564
申请日：2009-10-20
申请人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
发明人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
IPC分类号： H01L21/28
CPC分类号： H01L27/11573 , H01L21/28114 , H01L27/105 , H01L27/1052 , H01L29/42376
摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.
摘要翻译：提供了制造半导体器件的方法，所述方法包括在半导体衬底上形成依次层叠的第一电介质层，数据存储层和第二电介质层。具有暴露第二电介质层的第一区域的第一开口的掩模形成在第二电介质层上。形成填充至少一部分第一开口的栅电极。暴露第二电介质层的第二区域的第二开口通过蚀刻掩模形成，使得第二区域与第一区域间隔开。通过依次蚀刻第二介电层和数据存储层的暴露的第二区域来形成第二介质图案和数据存储图案。第二电介质图案形成为具有比栅电极的下表面更大的宽度。

23. 发明授权

US07557026B2 Contact structure and method of forming the same 有权
标题翻译：接触结构及其形成方法
公开(公告)号：US07557026B2
公开(公告)日：2009-07-07
申请号：US11711118
申请日：2007-02-27
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76804 , H01L21/76816 , H01L21/76897 , H01L27/11521
摘要： In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.
摘要翻译：在形成接触结构的方法中，第一和第二导电结构可以形成在下部结构上以彼此间隔开。可以在下部结构上形成绝缘层以覆盖第一和第二导电结构。露出第一导电结构的第一孔可以通过绝缘层形成。间隔件可以形成在第一孔的侧壁上。电耦合到第一导电结构的第一触点可以形成在具有形成间隔件的侧壁的第一孔中。可以去除位于间隔物之间的绝缘层的一部分，以形成暴露第二导电结构的第二孔。电耦合到第二导电结构的第二触点可以形成在第二孔中。

24. 发明申请

US20050167724A1 Semiconductor memory device with cylindrical storage electrode and method of manufacturing the same 有权
标题翻译：具有圆柱形存储电极的半导体存储器件及其制造方法
公开(公告)号：US20050167724A1
公开(公告)日：2005-08-04
申请号：US10992963
申请日：2004-11-18
申请人： Sung-Gil Choi , Sang-Sup Jeong
发明人： Sung-Gil Choi , Sang-Sup Jeong
IPC分类号： H01L21/8242 , H01L21/02 , H01L29/94 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.
摘要翻译：提供一种包括圆柱形存储电极的半导体存储器件及其制造方法。半导体存储器件包括形成在半导体衬底上的存储接触插塞的层间电介质层。圆柱形存储电极形成在层间电介质层之上，并且电连接到存储触点。间隔件联接到存储电极的外壁的预定部分。在存储电极和间隔物上形成电介质层，在电介质层的上方形成平板电极。因此，防止了存储电极的倾斜和位故障。

25. 发明申请

US20120040508A1 Method of Forming Semiconductor Device Having Self-Aligned Plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US20120040508A1
公开(公告)日：2012-02-16
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

26. 发明申请

US20090162989A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A LAYER SUSPENDED ACROSS A TRENCH 有权
标题翻译：使用横梁悬挂的层制造半导体器件的方法
公开(公告)号：US20090162989A1
公开(公告)日：2009-06-25
申请号：US12335831
申请日：2008-12-16
申请人： Du-Hyun Cho , Jong-Heui Song , Sang-Sup Jeong , Tae-Woo Kang , Seung-Joo Yoo
发明人： Du-Hyun Cho , Jong-Heui Song , Sang-Sup Jeong , Tae-Woo Kang , Seung-Joo Yoo
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.
摘要翻译：在形成沟槽的方法中，在衬底上形成以彼此分开第二宽度的第一宽度和第二图案彼此分开的第一图案。第二宽度比第一宽度宽。使用第一图案和第二图案蚀刻衬底，以形成具有第一深度的第一沟槽和具有第二深度的初步第二沟槽。形成牺牲层以填充第一图案之间的空间。使用牺牲层蚀刻衬底以形成具有比第二深度更深的第三深度的第二沟槽。

27. 发明申请

US20090117723A1 Methods of forming a conductive pattern in semiconductor devices and methods of manufacturing semiconductor devices having a conductive pattern 审中-公开
标题翻译：在半导体器件中形成导电图案的方法和制造具有导电图案的半导体器件的方法
公开(公告)号：US20090117723A1
公开(公告)日：2009-05-07
申请号：US12287945
申请日：2008-10-15
申请人： Jong-Kyu Kim , Bum-Soo Kim , Jong-Heui Song , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon
发明人： Jong-Kyu Kim , Bum-Soo Kim , Jong-Heui Song , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon
IPC分类号： H01L21/28 , H01L21/283
CPC分类号： H01L29/42324 , H01L21/02071 , H01L21/31122 , H01L21/31138 , H01L21/32139 , H01L27/11521 , H01L29/40114
摘要： In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.
摘要翻译：在半导体器件中形成导电图案的方法中，在衬底上形成包括金属的导电层。在导电层上设置包含碳的掩模，并且通过使用掩模作为蚀刻掩模蚀刻导电层，在基板上形成导电图案。通过氧等离子体灰化处理将掩模从导电图案中去除。导电图案的氧化部分减少。导电图案可以通过减少氧化部分而具有期望的电阻，以改善半导体器件的电特性和可靠性。

28. 发明授权

US07161205B2 Semiconductor memory device with cylindrical storage electrode and method of manufacturing the same 有权
标题翻译：具有圆柱形存储电极的半导体存储器件及其制造方法
公开(公告)号：US07161205B2
公开(公告)日：2007-01-09
申请号：US10992963
申请日：2004-11-18
申请人： Sung-Gil Choi , Sang-Sup Jeong
发明人： Sung-Gil Choi , Sang-Sup Jeong
IPC分类号： H01L29/72
CPC分类号： H01L28/91 , H01L27/10852
摘要： There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.
摘要翻译：提供一种包括圆柱形存储电极的半导体存储器件及其制造方法。半导体存储器件包括形成在半导体衬底上的存储接触插塞的层间电介质层。圆柱形存储电极形成在层间电介质层之上，并且电连接到存储触点。间隔件联接到存储电极的外壁的预定部分。在存储电极和间隔物上形成电介质层，在电介质层的上方形成平板电极。因此，防止了存储电极的倾斜和位故障。

29. 发明授权

US06617253B1 Plasma etching method using polymer deposition and method of forming contact hole using the plasma etching method 有权
标题翻译：使用聚合物沉积的等离子体蚀刻方法和使用等离子体蚀刻方法形成接触孔的方法
公开(公告)号：US06617253B1
公开(公告)日：2003-09-09
申请号：US09620022
申请日：2000-07-20
申请人： Chang-Woong Chu , Tae-Hyuk Ahn , Sang-Sup Jeong , Ji-Soo Kim
发明人： Chang-Woong Chu , Tae-Hyuk Ahn , Sang-Sup Jeong , Ji-Soo Kim
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76802
摘要： A plasma etching method using selective polymer deposition, and a method of forming a contact hole using the plasma etching method are provided. The plasma etching method uses a method of reinforcing an etch mask by selectively depositing polymer on only a photoresist pattern, which is an etch mask. That is, a dielectric film is plasma etched for a predetermined period of time using the photoresist pattern as an etch mask, and polymer is selectively deposited on only the photoresist pattern which is thinned by plasma etching, thereby forming a polymer layer. Following this, the dielectric film is plasma etched using the photoresist pattern and the polymer layer as a mask. Thus, dielectric film etching providing high resolution and an excellent profile can be performed using the thinned photoresist pattern as a mask, and a contact hole and a self-aligned contact hole each having a very high aspect ratio, and a self-aligned contact hole having an excellent profile, can be formed.
摘要翻译：提供了使用选择性聚合物沉积的等离子体蚀刻方法，以及使用等离子体蚀刻方法形成接触孔的方法。等离子体蚀刻方法使用通过仅在作为蚀刻掩模的光致抗蚀剂图案上选择性地沉积聚合物来增强蚀刻掩模的方法。也就是说，使用光致抗蚀剂图案作为蚀刻掩模，将电介质膜等离子体蚀刻预定的时间段，并且仅通过等离子体蚀刻而减薄的光致抗蚀剂图案上选择性地沉积聚合物，从而形成聚合物层。接下来，使用光致抗蚀剂图案和聚合物层作为掩模来等离子体蚀刻电介质膜。因此，可以使用减薄的光致抗蚀剂图案作为掩模，以及具有非常高的纵横比的接触孔和自对准接触孔以及自对准的接触孔来实现提供高分辨率和优异的轮廓的电介质膜蚀刻具有优异的外形，可以形成。

30. 发明授权

US06337275B1 Method for forming a self aligned contact in a semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US06337275B1
公开(公告)日：2002-01-08
申请号：US09334669
申请日：1999-06-17
申请人： Chang-Hyun Cho , Kyu-Hyun Lee , Jae-Goo Lee , Sang-Sup Jeong
发明人： Chang-Hyun Cho , Kyu-Hyun Lee , Jae-Goo Lee , Sang-Sup Jeong
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/76834
摘要： A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.
摘要翻译：半导体器件中的自对准接触（SAC）焊盘及其形成方法，其中SAC开口与单层栅极间隔物同时形成。在形成具有设置在其上的栅电极和覆盖层的堆叠栅极图案之后，在其上沉积栅极间隔物的绝缘层。然后在绝缘层上沉积层间绝缘层。层间绝缘层相对于覆盖层和绝缘层具有蚀刻选择性。然后在层间绝缘层中打开SAC，同时形成单层栅极间隔物。

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