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1. 发明申请

US20100099248A1 Methods of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20100099248A1
公开(公告)日：2010-04-22
申请号：US12588564
申请日：2009-10-20
申请人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
发明人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
IPC分类号： H01L21/28
CPC分类号： H01L27/11573 , H01L21/28114 , H01L27/105 , H01L27/1052 , H01L29/42376
摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.
摘要翻译：提供了制造半导体器件的方法，所述方法包括在半导体衬底上形成依次层叠的第一电介质层，数据存储层和第二电介质层。具有暴露第二电介质层的第一区域的第一开口的掩模形成在第二电介质层上。形成填充至少一部分第一开口的栅电极。暴露第二电介质层的第二区域的第二开口通过蚀刻掩模形成，使得第二区域与第一区域间隔开。通过依次蚀刻第二介电层和数据存储层的暴露的第二区域来形成第二介质图案和数据存储图案。第二电介质图案形成为具有比栅电极的下表面更大的宽度。

2. 发明授权

US08017485B2 Methods of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US08017485B2
公开(公告)日：2011-09-13
申请号：US12588564
申请日：2009-10-20
申请人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
发明人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28114 , H01L27/105 , H01L27/1052 , H01L29/42376
摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.
摘要翻译：提供了制造半导体器件的方法，所述方法包括在半导体衬底上形成依次层叠的第一电介质层，数据存储层和第二电介质层。具有暴露第二电介质层的第一区域的第一开口的掩模形成在第二电介质层上。形成填充至少一部分第一开口的栅电极。暴露第二电介质层的第二区域的第二开口通过蚀刻掩模形成，使得第二区域与第一区域间隔开。通过依次蚀刻第二介电层和数据存储层的暴露的第二区域来形成第二介质图案和数据存储图案。第二电介质图案形成为具有比栅电极的下表面更大的宽度。

3. 发明申请

US20090162989A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A LAYER SUSPENDED ACROSS A TRENCH 有权
标题翻译：使用横梁悬挂的层制造半导体器件的方法
公开(公告)号：US20090162989A1
公开(公告)日：2009-06-25
申请号：US12335831
申请日：2008-12-16
申请人： Du-Hyun Cho , Jong-Heui Song , Sang-Sup Jeong , Tae-Woo Kang , Seung-Joo Yoo
发明人： Du-Hyun Cho , Jong-Heui Song , Sang-Sup Jeong , Tae-Woo Kang , Seung-Joo Yoo
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.
摘要翻译：在形成沟槽的方法中，在衬底上形成以彼此分开第二宽度的第一宽度和第二图案彼此分开的第一图案。第二宽度比第一宽度宽。使用第一图案和第二图案蚀刻衬底，以形成具有第一深度的第一沟槽和具有第二深度的初步第二沟槽。形成牺牲层以填充第一图案之间的空间。使用牺牲层蚀刻衬底以形成具有比第二深度更深的第三深度的第二沟槽。

4. 发明授权

US08003487B2 Methods of manufacturing a semiconductor device using a layer suspended across a trench 有权
标题翻译：使用悬挂在沟槽上的层的半导体器件的制造方法
公开(公告)号：US08003487B2
公开(公告)日：2011-08-23
申请号：US12335831
申请日：2008-12-16
申请人： Du-Hyun Cho , Jong-Heui Song , Sang-Sup Jeong , Tae-Woo Kang , Seung-Joo Yoo
发明人： Du-Hyun Cho , Jong-Heui Song , Sang-Sup Jeong , Tae-Woo Kang , Seung-Joo Yoo
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.
摘要翻译：在形成沟槽的方法中，在衬底上形成以彼此分开第二宽度的第一宽度和第二图案彼此分开的第一图案。第二宽度比第一宽度宽。使用第一图案和第二图案蚀刻衬底，以形成具有第一深度的第一沟槽和具有第二深度的初步第二沟槽。形成牺牲层以填充第一图案之间的空间。使用牺牲层蚀刻衬底以形成具有比第二深度更深的第三深度的第二沟槽。

5. 发明申请

US20070047304A1 Non-volatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070047304A1
公开(公告)日：2007-03-01
申请号：US11508919
申请日：2006-08-24
申请人： Seong-Soo Lee , Young-Wook Park , Jang-Bin Yim , Bum-Su Kim , Du-Hyun Cho
发明人： Seong-Soo Lee , Young-Wook Park , Jang-Bin Yim , Bum-Su Kim , Du-Hyun Cho
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： In a non-volatile memory device having a relatively high operation performance and a method of manufacturing the same, a substrate may be prepared to include an active region on which a conductive structure is located and defined by a field region in which an isolation layer is formed. A tunnel oxide layer may be formed on the active region of the substrate. A floating gate pattern may be formed on the tunnel oxide layer, and may include a lower part having a first width that is formed on the tunnel oxide layer and an upper part having a second width that is formed on the lower part, where the second width is substantially smaller than the first width. A dielectric layer pattern may be formed on the floating gate pattern, and a control gate pattern may be formed on the dielectric layer pattern. Accordingly, the non-volatile memory device may have an improved efficiency in programming and erasing data.
摘要翻译：在具有较高操作性能的非易失性存储器件及其制造方法中，衬底可以被制备为包括有源区，导电结构位于该有源区上，该区域由隔离层为形成。可以在衬底的有源区上形成隧道氧化物层。可以在隧道氧化物层上形成浮置栅极图案，并且可以包括形成在隧道氧化物层上的第一宽度的下部和形成在下部的第二宽度的上部，宽度基本上小于第一宽度。可以在浮置栅极图案上形成电介质层图案，并且可以在电介质层图案上形成控制栅极图案。因此，非易失性存储器件可以提高编程和擦除数据的效率。

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