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1. 发明申请

US20060046382A1 Method of forming a capacitor for a semiconductor device 审中-公开
标题翻译：形成用于半导体器件的电容器的方法
公开(公告)号：US20060046382A1
公开(公告)日：2006-03-02
申请号：US11206418
申请日：2005-08-17
申请人： Kuk-Han Yoon , Sang-Sup Jeong , Sung-Gil Choi , Jong-Kyu Kim
发明人： Kuk-Han Yoon , Sang-Sup Jeong , Sung-Gil Choi , Jong-Kyu Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/91
摘要： In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.
摘要翻译：在一个实施例中，示出了形成其结构稳定性提高的半导体器件的电容器的方法。圆柱形存储电极在基板上以矩阵图案形成，该基板包括其中具有触点的绝缘中间层，使得模具层围绕圆柱形存储电极。牺牲塞在这些电极内形成有盖。通过部分蚀刻模具层，在蚀刻的模具层和圆柱形存储电极上形成稳定层。蚀刻稳定层，直到牺牲塞被暴露，从而形成间隔物。尽管完全去除了牺牲塞和模具层，但是间隔件被部分地移除，从而形成用于支撑彼此相邻的相邻存储电极的稳定构件。因此，提高了电容器的结构稳定性。

2. 发明授权

US08704283B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08704283B2
公开(公告)日：2014-04-22
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

3. 发明申请

US20080096378A1 Contact structure and method of forming the same 有权
标题翻译：接触结构及其形成方法
公开(公告)号：US20080096378A1
公开(公告)日：2008-04-24
申请号：US11711118
申请日：2007-02-27
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76804 , H01L21/76816 , H01L21/76897 , H01L27/11521
摘要： In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.
摘要翻译：在形成接触结构的方法中，第一和第二导电结构可以形成在下部结构上以彼此间隔开。可以在下部结构上形成绝缘层以覆盖第一和第二导电结构。露出第一导电结构的第一孔可以通过绝缘层形成。间隔件可以形成在第一孔的侧壁上。电耦合到第一导电结构的第一触点可以形成在具有形成间隔件的侧壁的第一孔中。可以去除位于间隔物之间的绝缘层的一部分，以形成暴露第二导电结构的第二孔。电耦合到第二导电结构的第二触点可以形成在第二孔中。

4. 发明申请

US20100237466A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20100237466A1
公开(公告)日：2010-09-23
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L29/92
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

5. 发明授权

US07557026B2 Contact structure and method of forming the same 有权
标题翻译：接触结构及其形成方法
公开(公告)号：US07557026B2
公开(公告)日：2009-07-07
申请号：US11711118
申请日：2007-02-27
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76804 , H01L21/76816 , H01L21/76897 , H01L27/11521
摘要： In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.
摘要翻译：在形成接触结构的方法中，第一和第二导电结构可以形成在下部结构上以彼此间隔开。可以在下部结构上形成绝缘层以覆盖第一和第二导电结构。露出第一导电结构的第一孔可以通过绝缘层形成。间隔件可以形成在第一孔的侧壁上。电耦合到第一导电结构的第一触点可以形成在具有形成间隔件的侧壁的第一孔中。可以去除位于间隔物之间的绝缘层的一部分，以形成暴露第二导电结构的第二孔。电耦合到第二导电结构的第二触点可以形成在第二孔中。

6. 发明申请

US20050167724A1 Semiconductor memory device with cylindrical storage electrode and method of manufacturing the same 有权
标题翻译：具有圆柱形存储电极的半导体存储器件及其制造方法
公开(公告)号：US20050167724A1
公开(公告)日：2005-08-04
申请号：US10992963
申请日：2004-11-18
申请人： Sung-Gil Choi , Sang-Sup Jeong
发明人： Sung-Gil Choi , Sang-Sup Jeong
IPC分类号： H01L21/8242 , H01L21/02 , H01L29/94 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.
摘要翻译：提供一种包括圆柱形存储电极的半导体存储器件及其制造方法。半导体存储器件包括形成在半导体衬底上的存储接触插塞的层间电介质层。圆柱形存储电极形成在层间电介质层之上，并且电连接到存储触点。间隔件联接到存储电极的外壁的预定部分。在存储电极和间隔物上形成电介质层，在电介质层的上方形成平板电极。因此，防止了存储电极的倾斜和位故障。

7. 发明申请

US20090117723A1 Methods of forming a conductive pattern in semiconductor devices and methods of manufacturing semiconductor devices having a conductive pattern 审中-公开
标题翻译：在半导体器件中形成导电图案的方法和制造具有导电图案的半导体器件的方法
公开(公告)号：US20090117723A1
公开(公告)日：2009-05-07
申请号：US12287945
申请日：2008-10-15
申请人： Jong-Kyu Kim , Bum-Soo Kim , Jong-Heui Song , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon
发明人： Jong-Kyu Kim , Bum-Soo Kim , Jong-Heui Song , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon
IPC分类号： H01L21/28 , H01L21/283
CPC分类号： H01L29/42324 , H01L21/02071 , H01L21/31122 , H01L21/31138 , H01L21/32139 , H01L27/11521 , H01L29/40114
摘要： In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.
摘要翻译：在半导体器件中形成导电图案的方法中，在衬底上形成包括金属的导电层。在导电层上设置包含碳的掩模，并且通过使用掩模作为蚀刻掩模蚀刻导电层，在基板上形成导电图案。通过氧等离子体灰化处理将掩模从导电图案中去除。导电图案的氧化部分减少。导电图案可以通过减少氧化部分而具有期望的电阻，以改善半导体器件的电特性和可靠性。

8. 发明授权

US07161205B2 Semiconductor memory device with cylindrical storage electrode and method of manufacturing the same 有权
标题翻译：具有圆柱形存储电极的半导体存储器件及其制造方法
公开(公告)号：US07161205B2
公开(公告)日：2007-01-09
申请号：US10992963
申请日：2004-11-18
申请人： Sung-Gil Choi , Sang-Sup Jeong
发明人： Sung-Gil Choi , Sang-Sup Jeong
IPC分类号： H01L29/72
CPC分类号： H01L28/91 , H01L27/10852
摘要： There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.
摘要翻译：提供一种包括圆柱形存储电极的半导体存储器件及其制造方法。半导体存储器件包括形成在半导体衬底上的存储接触插塞的层间电介质层。圆柱形存储电极形成在层间电介质层之上，并且电连接到存储触点。间隔件联接到存储电极的外壁的预定部分。在存储电极和间隔物上形成电介质层，在电介质层的上方形成平板电极。因此，防止了存储电极的倾斜和位故障。

9. 发明授权

US08507353B2 Method of forming semiconductor device having self-aligned plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US08507353B2
公开(公告)日：2013-08-13
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

10. 发明申请

US20130009226A1 DRAM DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译： DRAM器件及其制造方法
公开(公告)号：US20130009226A1
公开(公告)日：2013-01-10
申请号：US13540816
申请日：2012-07-03
申请人： Jong-Chul Park , Byung-Jin Kang , Sang-Sup Jeong
发明人： Jong-Chul Park , Byung-Jin Kang , Sang-Sup Jeong
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L21/76816 , H01L21/76897 , H01L27/10855 , H01L27/10876 , H01L27/10894
摘要： A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.
摘要翻译： DRAM器件包括具有岛形状的有源区和掩埋栅极图案的衬底。掩模图案位于掩埋栅极图案的部分之间的衬底的上表面部分之上。封盖绝缘层填充掩模图案的部分之间的间隙。第一焊盘接触件穿透封盖绝缘层和掩模图案，并且与有源区域中的基板的第一部分接触。第二焊盘触点位于封盖绝缘层下方，并且接触位于第一焊盘触点两侧的有源区域中的基板的第二部分。间隔物位于第一和第二焊盘触点之间，以使第一和第二焊盘触点绝缘。提供了构造成与第一焊盘触点电连接的位线和被配置为与第二焊盘触点电连接的电容器。

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