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21. 发明授权

US5008209A Method of manufacturing a semiconductor device including outdiffusion from polysilicon rims 失效
标题翻译：制造半导体器件的方法，其包括从多晶硅边缘扩散
公开(公告)号：US5008209A
公开(公告)日：1991-04-16
申请号：US463183
申请日：1990-01-10
申请人： Johannes A. Appels , Henricus G. R. Maas
发明人： Johannes A. Appels , Henricus G. R. Maas
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/06 , H01L29/73 , H01L29/78
CPC分类号： H01L21/76838 , H01L23/522 , H01L23/53271 , H01L2924/0002 , Y10S148/131
摘要： A method of manufacturing a semiconductor device is set forth using anisotropic etching techniques, such as plasma etching and reactive ion etching to obtain interconnection patterns having accurately defined rims. Various different kinds of transistors can be manufacturing in the same semiconductor body using these techniques.
摘要翻译：使用诸如等离子体蚀刻和反应离子蚀刻之类的各向异性蚀刻技术来提供制造半导体器件的方法，以获得具有精确定义的边缘的互连图案。可以使用这些技术在相同的半导体主体中制造各种不同种类的晶体管。

22. 发明授权

US4907049A Charge-coupled semiconductor device having an improved electrode structure 失效
标题翻译：具有改进的电极结构的电荷耦合半导体器件
公开(公告)号：US4907049A
公开(公告)日：1990-03-06
申请号：US385928
申请日：1989-07-27
申请人： Jan W. Slotboom , Henricus G. R. Maas , Kazimierz Osinki , Geert J. T. Davids
发明人： Jan W. Slotboom , Henricus G. R. Maas , Kazimierz Osinki , Geert J. T. Davids
IPC分类号： H01L29/762 , H01L21/339 , H01L27/10 , H01L29/423 , H01L29/76 , H01L29/772
CPC分类号： H01L29/66954 , H01L29/42396
摘要： A charge-coupled semiconductor device has a plurality of silicon electrodes for storing and transporting information-carrying charge, which electrodes are located on an insulating layer and are mutually separated by grooves having a width of at most 1 .mu.m. According to the invention, transfer electrodes are arranged in the grooves, these electrodes being coplanar with the remaining electrodes. The thickness of the insulating layer under the transfer electrodes is substantially equal to that under the storage electrodes. The invention also relates to a method of manufacturing a semiconductor device having such an electrode system.
摘要翻译：电荷耦合半导体器件具有用于存储和传送信息传送电荷的多个硅电极，这些电极位于绝缘层上并且由宽度至多为1μm的沟槽相互分离。根据本发明，转移电极布置在凹槽中，这些电极与剩余的电极共面。传输电极下面的绝缘层的厚度基本上等于存储电极下方的厚度。本发明还涉及制造具有这种电极系统的半导体器件的方法。

23. 发明授权

US06177707B1 Semiconductor device comprising a glass supporting body onto which a substrate with semiconductor elements and a metalization is attached by means of an adhesive 有权
标题翻译：包括玻璃支撑体的半导体装置，借助于粘合剂将具有半导体元件的基板和金属化附着在该玻璃支撑体上
公开(公告)号：US06177707B1
公开(公告)日：2001-01-23
申请号：US09258430
申请日：1999-02-26
申请人： Ronald Dekker , Henricus G. R. Maas , Maria H. W. A. Van Deurzen
发明人： Ronald Dekker , Henricus G. R. Maas , Maria H. W. A. Van Deurzen
IPC分类号： H01L2910
CPC分类号： H01L21/84 , H01L21/7624 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/48463 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： A thin film semiconductor device includes a glass supporting body having thereon an insulating substrate which is attached thereto by a layer of adhesive material. On the surface of the substrate facing the supporting body is a layer of semiconductor material which includes therein a semiconductor element, such surface further having thereon a metalization pattern of conductor tracks. An insulating layer is additionally provided between the metalization pattern and the adhesive layer, and has a dielectric constant &egr;r below 3 and a thickness in the range of approximately 20 &mgr;m to 60 &mgr;m. By virtue of such additional layer, parasitic capacitanees between the metalization pattern and an envelope in which the device is included or a printed circuit board on which the device is mounted are reduced substantially, thereby reducing the power consumption of the device.
摘要翻译：薄膜半导体器件包括玻璃支撑体，其上具有通过粘合剂材料层附接到其上的绝缘基底。在面向支撑体的基板的表面上是包括半导体元件的半导体材料层，该表面还具有导体轨迹的金属化图案。在金属化图案和粘合剂层之间另外设置绝缘层，其介电常数ε为3以下，厚度为20μm〜60μm左右。由于这种附加层，金属化图案与其中包含器件的封套之间的寄生电容或其上安装器件的印刷电路板被大大减小，从而降低了器件的功耗。

24. 发明授权

US5739591A Semiconductor device with a carrier body on which a substrate with a semiconductor element is fastened by means of a glue layer and on which a pattern of conductor tracks is fastened 失效
标题翻译：具有载体的半导体器件，其上具有半导体元件的衬底通过胶层紧固，并且其上固定有导体轨迹的图案
公开(公告)号：US5739591A
公开(公告)日：1998-04-14
申请号：US889716
申请日：1997-07-08
申请人： Ronald Dekker , Henricus G. R. Maas
发明人： Ronald Dekker , Henricus G. R. Maas
IPC分类号： H01L27/04 , H01L21/58 , H01L21/68 , H01L21/76 , H01L21/822 , H01L23/482 , H01L23/528 , H01L23/48
CPC分类号： H01L21/6835 , H01L23/4825 , H01L24/29 , H01L24/83 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2224/1134 , H01L2224/24225 , H01L2224/2919 , H01L2224/8319 , H01L2224/8385 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01058 , H01L2924/01072 , H01L2924/01079 , H01L2924/0665 , H01L2924/07802 , H01L2924/1305 , H01L2924/1306 , H01L2924/19041
摘要： A semiconductor device with a carrier body on which a substrate is fastened by means of a glue layer, which substrate is provided at its first side facing the carrier body with a semiconductor element and with a pattern of conductor tracks comprising contact electrodes for external contacting from the second side of the substrate facing away from the carrier body. The substrate is provided with windows at the areas of the contact electrodes for external contacting from the second side. The process steps preceding the gluing of the substrate to the carrier body are carried out in a clean room suitable for the manufacture of semiconductor elements, whereas the remaining process steps are preferably carried out in a final mounting room. Expensive lithographical equipment need not be available in both rooms, because the comparatively large windows can be formed by means of a simple contact mask.
摘要翻译：一种具有载体的半导体器件，其上通过胶层将衬底紧固在该衬底上，该衬底在其与载体主体相对的第一面处设置有半导体元件，并且具有包括用于外部接触的接触电极的导体轨迹图案衬底的背离载体的第二面。基板在接触电极的区域处设置有用于从第二侧进行外部接触的窗口。在将衬底粘合到载体上之前的工艺步骤在适于制造半导体元件的洁净室中进行，而其余工艺步骤优选在最终安装室中进行。两个房间都不需要昂贵的光刻设备，因为可以通过简单的接触面罩形成比较大的窗户。

25. 发明授权

US5399899A Bipolar epitaxial cascode with low-level base connection 失效
标题翻译：具有低电平基极连接的双极外延级共源共栅
公开(公告)号：US5399899A
公开(公告)日：1995-03-21
申请号：US173839
申请日：1993-12-27
申请人： Ronald Dekker , Henricus G. R. Maas , Dirk J. Gravesteijn , Martinus P. J. G. Versleijen
发明人： Ronald Dekker , Henricus G. R. Maas , Dirk J. Gravesteijn , Martinus P. J. G. Versleijen
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/082 , H01L29/73 , H01L29/72
CPC分类号： H01L27/0825
摘要： A semiconductor device with a semiconductor body (1) is provided with a first and a second bipolar transistor (T1, T2, respectively) in a cascode configuration, in which the semiconductor body (1) comprises, in that order, a collector region (10) and a base region (11) of the first transistor (T1), a region (12) which forms both an emitter region of the first transistor (T1) and a collector region of the second transistor (T2), a space charge region (13), and a base region (14) and emitter region (15) of the second transistor (T2), while the regions form pn junctions with one another which extend parallel to a main surface (2) of the semiconductor body (1). The base region (14) and the emitter region (15) of the second transistor (T2) adjoin a main surface (3) of the semiconductor body (1). According to the invention, a depression (4) is provided in this main surface (3), cutting through the emitter region (12) of the first transistor (T1) which at the same time is the collector region (12) of the second transistor (T2), the space charge region (13), and the base region (14) of the second transistor (T2) and laterally bounding these; regions, while a connection electrode (B1) for the base region (11) of the first transistor (T1) is provided in the depression (4). No latch-up by a parasitic transistor then takes place in the device.
摘要翻译：具有半导体本体（1）的半导体器件以共成型结构设置有第一和第二双极晶体管（T1，T2），其中半导体主体（1）依次包括集电极区域 10）和第一晶体管（T1）的基极区域（11），形成第一晶体管（T1）的发射极区域和第二晶体管（T2）的集电极区域的区域（12），空间电荷区域（13）以及第二晶体管（T2）的基极区域（14）和发射极区域（15），同时区域形成彼此平行于半导体主体的主表面（2）延伸的pn结（ 1）。第二晶体管（T2）的基极区域（14）和发射极区域（15）与半导体本体（1）的主表面（3）相邻。根据本发明，在该主表面（3）中设置凹陷（4），切割第一晶体管（T1）的发射极区域（12），同时是第二晶体管的集电极区域（12）晶体管（T2），空间电荷区域（13）和第二晶体管（T2）的基极区域（14）并且横向地限制它们; 区域，而在第一晶体管（T1）的基极区域（11）的连接电极（B1）设置在凹部（4）中。然后在器件中不会发生寄生晶体管的闩锁。

26. 发明授权

US4825267A Field effect transistor having self-registering source and drain regions to minimize capacitances 失效
标题翻译：场效应晶体管具有自对准源极和漏极区域以最小化电容
公开(公告)号：US4825267A
公开(公告)日：1989-04-25
申请号：US721123
申请日：1985-04-08
申请人： Henricus G. R. Maas
发明人： Henricus G. R. Maas
IPC分类号： H01L27/10 , H01L21/205 , H01L21/285 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/45 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/28525 , H01L27/10823 , H01L29/456
摘要： A field effect transistor is formed with a source and drain which are realized partly as a semiconductor region and a semiconductor body, and partly as a portion of a deposited epitaxial layer. A recess is formed into a substrate of the semiconductor body between the source and drain, and a channel region underlies the recess in the substrate. As a result of this construction, the channel length is independent of variations in the thickness of the epitaxial layer, and the stray capacitances from source and drain to the substrate are small. Moreover, a conductor pattern, separated from the epitaxial layer by an insulating layer, may extend to be on the connection zones of the source and drain, which involves a high packing density. The epitaxial layer, moreover, comprises extra wiring tracks. This gives a great freedom in design.
摘要翻译：场效应晶体管形成有源极和漏极，其部分地被实现为半导体区域和半导体本体，并且部分地被实现为沉积的外延层的一部分。在源极和漏极之间形成半导体本体的衬底中的凹槽，并且沟道区域位于衬底中的凹部下方。作为这种结构的结果，沟道长度与外延层的厚度的变化无关，并且从源极和漏极到衬底的杂散电容很小。此外，通过绝缘层与外延层分离的导体图案可以延伸到源极和漏极的连接区上，其包括高堆积密度。此外，外延层包括额外的布线轨道。这给设计带来了很大的自由。

27. 发明授权

US4689872A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4689872A
公开(公告)日：1987-09-01
申请号：US771930
申请日：1985-09-03
申请人： Johannes A. Appels , Henricus G. R. Maas
发明人： Johannes A. Appels , Henricus G. R. Maas
IPC分类号： H01L29/78 , H01L21/033 , H01L21/225 , H01L21/331 , H01L21/336 , H01L23/532 , H01L29/73 , H01L29/732 , H01L21/22 , H01L21/265 , H01L21/318
CPC分类号： H01L29/66272 , H01L21/0337 , H01L21/2257 , H01L23/53271 , H01L2924/0002 , Y10S148/011 , Y10S148/051 , Y10S148/103 , Y10S438/911
摘要： For providing semiconductor zones (16, 18, 26) and contact metallization (19, 27) within an opening (9) in a self-registered manner, which opening is provided along its edge with polycrystalline connection parts (10) separated by an insulating material (15) from the metallization (19, 27), a protective layer (11) is formed which is maintained within the opening (9)until within this opening (9) the connection parts (10) are formed by anisotropic etching from a uniform layer of polycrystalline semiconductor material (10). The method is suitable for the manufacture of both bipolar transistors and field effect transistors.
摘要翻译：为了以自我注册的方式在开口（9）内提供半导体区域（16,18,26）和接触金属化（19,27），所述开口沿着其边缘设置有由绝缘体分隔的多晶连接部分（10）从金属化（19,27）的材料（15）形成保护层（11），其保持在开口（9）内，直到在该开口（9）内，连接部分（10）通过各向异性蚀刻从均匀的多晶半导体材料层（10）。该方法适用于制造双极晶体管和场效应晶体管。

28. 发明授权

US4636826A Charge coupled devices having narrow coplanar silicon electrodes 失效
标题翻译：具有窄共面硅电极的电荷耦合器件
公开(公告)号：US4636826A
公开(公告)日：1987-01-13
申请号：US802499
申请日：1985-11-27
申请人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
发明人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
IPC分类号： H01L29/762 , H01L21/033 , H01L21/339 , H01L27/10 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66954 , H01L21/033
摘要： In a semiconductor device, for example a SPS memory having narrow coplanar silicon electrodes, the electrodes are formed by etching grooves or slots having a width in the submicron range into a polycrystalline silicon layer with the slot width being defined by the oxidized edge of a silicon auxiliary layer. The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. The covered electrodes are first interconnected pairwise, whereupon they are separated from each other, and are provided with self-aligned contact windows. Thus, the very narrow electrodes can be contracted without technological problems and memory cells of very small dimensions are provided.

29. 发明授权

US4619039A Method of manufacturing a semiconductor device and device manufactured by the use of the method 失效
标题翻译：通过使用该方法制造半导体器件和器件的方法
公开(公告)号：US4619039A
公开(公告)日：1986-10-28
申请号：US657644
申请日：1984-10-04
申请人： Henricus G. R. Maas , Jan W. Slotboom , Johannes A. Appels , Kazimierz Osinski
发明人： Henricus G. R. Maas , Jan W. Slotboom , Johannes A. Appels , Kazimierz Osinski
IPC分类号： H01L29/762 , H01L21/339 , H01L29/417 , H01L29/423 , H01L29/76 , H01L29/772 , H01L21/90
CPC分类号： H01L29/66954 , H01L29/42396 , Y10S438/911
摘要： A method of manufacturing a semiconductor device having narrow, coplanar, silicon electrodes which are separated from each other by grooves or slots having a width in the submicron range. The electrodes are alternatively covered by an oxide and by an oxidation-preventing layer, such as silicon nitride. According to the invention, a first and second electrode which are both covered with one of these layers, and which enclose a third electrode covered by the other of these layers, are first interconnected inside a connection region. Two of the three electrodes are separated from the connection region by etching. By selective etching, overlapping contact windows are provided on all three electrodes, and inside the contact windows etching of the groove is omitted.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有窄的，共面的硅电极，它们通过宽度在亚微米范围内的槽或狭缝彼此分开。电极交替地由氧化物和诸如氮化硅的防氧化层覆盖。根据本发明，第一和第二电极都被这些层中的一个覆盖，并且包围由这些层中的另一个覆盖的第三电极首先在连接区域内互连。三个电极中的两个通过蚀刻与连接区域分离。通过选择性蚀刻，在所有三个电极上设置重叠的接触窗口，并且在接触窗口的内部省略了凹槽的蚀刻。

30. 发明授权

US4514251A Method of manufacturing a semiconductor device, in which patterns are formed in a layer of silicon nitride by means of ion implantation 失效
标题翻译：制造半导体器件的方法，其中通过离子注入在氮化硅层中形成图案
公开(公告)号：US4514251A
公开(公告)日：1985-04-30
申请号：US595092
申请日：1984-03-30
申请人： Alfred H. van Ommen , Henricus G. R. Maas , Johannes A. Appels , Wilhelmus J. M. J. Josquin
发明人： Alfred H. van Ommen , Henricus G. R. Maas , Johannes A. Appels , Wilhelmus J. M. J. Josquin
IPC分类号： H01L21/306 , H01L21/311 , H01L21/3115 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31155 , H01L21/31111 , H01L21/31116
摘要： In a method of manufacturing a semiconductor device, ions are implanted into a layer of silicon nitride over a part of its surface, and the layer is then subjected to an etching treatment. According to the present invention, before the etching treatment takes place, but after the ion implantation, the layer is subjected to a heat treatment in which the implanted part of the layer obtains a higher resistance to etching than the non-implanted part. The heat treatment occurs at temperatures above 750.degree. C. Thus, a negative image of a patterned ion irradiation can be formed in the silicon nitride layer. As a result, the number of cases in which an etching or oxidation mask can be formed in a silicon nitride layer without using additional mask is considerably increased.
摘要翻译：在制造半导体器件的方法中，将离子注入到其表面的一部分上的氮化硅层中，然后对该层进行蚀刻处理。根据本发明，在进行蚀刻处理之前，但是在离子注入之后，对该层进行热处理，其中该层的注入部分比非植入部分获得更高的耐蚀刻性。热处理发生在高于750℃的温度下。因此，可以在氮化硅层中形成图案化离子照射的负像。结果，在不使用附加掩模的情况下可以在氮化硅层中形成蚀刻或氧化掩模的情况大大增加。

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