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21. 发明申请

US20090006782A1 APPARATUS AND METHOD FOR ACCESSING A MEMORY DEVICE 失效
标题翻译：用于访问存储器件的装置和方法
公开(公告)号：US20090006782A1
公开(公告)日：2009-01-01
申请号：US12143889
申请日：2008-06-23
申请人： Peter Buchmann , Martin Leo Schmatz , Jan Van Lunteren
发明人： Peter Buchmann , Martin Leo Schmatz , Jan Van Lunteren
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F12/0223 , G11C15/00
摘要： An apparatus and a corresponding method for coupling a memory device being addressable by means of an address space to a processing unit, the apparatus consisting: a first memory access unit being adapted for receiving a memory address from the processing unit and for accessing the memory device by the received memory address; a second memory access unit being adapted for receiving content data (an input key) from the processing unit and for controlling a search for the received content data in the memory device, and an allocation unit for allocating a first part of the address space of the memory device to the first memory access unit and a second part of the address space of the memory device to the second memory access unit. A storage medium to perform coupling a memory device being addressable by means of an address space to a processing unit is also provided.
摘要翻译：一种用于将可通过地址空间寻址的存储器件耦合到处理单元的装置和相应方法，所述装置包括：第一存储器存取单元，适于从所述处理单元接收存储器地址并访问存储器件由接收的存储器地址; 第二存储器存取单元，其适于从所述处理单元接收内容数据（输入密钥），并且用于控制对所述存储器件中的所接收的内容数据的搜索;以及分配单元，用于分配所述存储器存储单元的地址空间的第一部分存储器设备到第一存储器存取单元以及存储器件的地址空间的第二部分到第二存储器存取单元。还提供了一种用于通过地址空间将可寻址的存储器件耦合到处理单元的存储介质。

22. 发明申请

US20080228798A1 Method and apparatus for deep packet processing 有权
标题翻译：深度数据包处理的方法和装置
公开(公告)号：US20080228798A1
公开(公告)日：2008-09-18
申请号：US12123183
申请日：2008-05-19
申请人： Jan Van Lunteren
发明人： Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： H04L63/02 , H04L45/7457 , H04L69/12 , H04L69/22
摘要： A method and apparatus for deep packet processing including a parsing and a searching method supported by a data structure storing the state-transition rules in the state-transition rule tables of a programmable state machine for parsing. The state-transition rule table is then compressed using the BaRT compression algorithm. Each transition rule comprises a test value, a test mask and a next state field. In a second embodiment the state-transition rule table is split into more than one state-transition rule table corresponding to disjoints state spaces, thus allowing more flexibility in the use of storage space. Finally a parsing and searching method can be implemented using the same hardware. The searching and parsing methods can be implemented alternatively or in any combination at wire-speed.
摘要翻译：一种用于深度分组处理的方法和装置，包括由可编程状态机的状态转换规则表中存储状态转换规则的数据结构支持的解析和搜索方法，用于解析。然后使用BaRT压缩算法压缩状态转换规则表。每个转换规则包括测试值，测试掩码和下一个状态字段。在第二实施例中，状态转移规则表被分成与不相交状态空间相对应的多于一个的状态转移规则表，从而允许使用存储空间的更大的灵活性。最后，可以使用相同的硬件实现解析和搜索方法。搜索和解析方法可以以线速交替地或以任何组合来实现。

23. 发明申请

US20070283300A1 Method and System for Changing a Description for a State Transition Function of a State Machine Engine 失效
标题翻译：用于更改状态机引擎的状态转换功能的描述的方法和系统
公开(公告)号：US20070283300A1
公开(公告)日：2007-12-06
申请号：US11740487
申请日：2007-04-26
申请人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
发明人： Rolf Fritz , Markus Kaltenbach , Ulrich Mayer , Thomas Pflueger , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.
摘要翻译：本发明涉及一种用于设计和实施状态机发动机的方法和系统。第一约束检查步骤检查由设计者创建的状态转换函数，以抵制由实施技术施加的约束，以便检测与约束相冲突的状态转换函数的所有部分。随后的冲突解决步骤尝试通过调查如何修改原始状态转换功能以满足所有约束来确定满足冲突约束的一种或多种建议方式。最后的演示和选择步骤为设计者提供了约束检查和建议修改的文本和/或图形结果。可以交互接受修改，也可以手动更改状态转换功能。在后一种情况下，将通过约束检查步骤再次开始处理修改的状态转换功能。

24. 发明授权

US08799188B2 Algorithm engine for use in a pattern matching accelerator 有权
标题翻译：用于模式匹配加速器的算法引擎
公开(公告)号：US08799188B2
公开(公告)日：2014-08-05
申请号：US13023003
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Russell D. Hoover , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Russell D. Hoover , Jan Van Lunteren
IPC分类号： G06F15/18
CPC分类号： G06N5/025
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

25. 发明授权

US08447749B2 Local results processor for use in a pattern matching accelerator 失效
标题翻译：本地结果处理器用于模式匹配加速器
公开(公告)号：US08447749B2
公开(公告)日：2013-05-21
申请号：US13022967
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06F11/1402
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

26. 发明授权

US08427201B2 Local result processor 失效
标题翻译：本地结果处理器
公开(公告)号：US08427201B2
公开(公告)日：2013-04-23
申请号：US13070864
申请日：2011-03-24
申请人： Jan Van Lunteren
发明人： Jan Van Lunteren
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A system includes a register, a first logical function portion, the first logical function portion operative to receive a first numerical value from the register, perform a first logical function with the first numerical value, and output a second numerical value, a second logical function portion, the second logical function portion operative to receive the first numerical value from the register, perform a second logical function with the first numerical value, and output a third numerical value, and a control logic portion, the control logic portion operative to receive the first numerical value from the register, determine whether the first numerical value includes a code associated with either the first logical function or the second logical function, and responsive to determining that the code is associated with the first logical function, and direct the output of the second numerical value to an input of the register.
摘要翻译：一种系统包括寄存器，第一逻辑功能部分，第一逻辑功能部分，用于从寄存器接收第一数值，执行具有第一数值的第一逻辑函数，并输出第二数值，第二逻辑函数所述第二逻辑功能部分用于从所述寄存器接收所述第一数值，执行具有所述第一数值的第二逻辑功能，并输出第三数值，以及控制逻辑部分，所述控制逻辑部分用于接收所述第一数值，确定所述第一数值是否包括与所述第一逻辑功能或所述第二逻辑功能相关联的代码，并且响应于确定所述代码与所述第一逻辑功能相关联，并且指示所述第一逻辑功能的输出第二数值到寄存器的输入。

27. 发明申请

US20120284222A1 COMPILING PATTERN CONTEXTS TO SCAN LANES UNDER INSTRUCTION EXECUTION CONSTRAINTS 有权
标题翻译：根据指令执行规则编写模式到扫描范围
公开(公告)号：US20120284222A1
公开(公告)日：2012-11-08
申请号：US13098772
申请日：2011-05-02
申请人： Kubilay Atasu , Florian Dorfler , Christoph Hagleitner , Jan Van Lunteren
发明人： Kubilay Atasu , Florian Dorfler , Christoph Hagleitner , Jan Van Lunteren
IPC分类号： G06N5/02
CPC分类号： H04L63/1408
摘要： A technique for determining scan lanes is provided. For a set of patterns, a number of scan lanes is estimated to be utilized on an accelerator. The number of the scan lanes estimated for the set of patterns is iteratively incremented to optimize a throughput of the accelerator. The set of patterns is distributed to the number of the scan lanes as a distribution, and each one of the scan lanes has a predetermined number of engines. A size of a memory space is evaluated that is needed for the distribution to distribute the set of patterns onto the number of scan lanes.
摘要翻译：提供了一种用于确定扫描通道的技术。对于一组模式，估计在加速器上使用多个扫描通道。针对该组模式估计的扫描通道的数量被迭代地增加以优化加速器的吞吐量。该组图案被分配到扫描通道的数量作为分布，并且每个扫描通道具有预定数量的引擎。评估存储器空间的大小，以便将该组图案分配到扫描通道数上。

28. 发明申请

US20120203756A1 LOCAL RESULTS PROCESSOR FOR USE IN A PATTERN MATCHING ACCELERATOR 失效
标题翻译：用于模式匹配加速器的本地结果处理器
公开(公告)号：US20120203756A1
公开(公告)日：2012-08-09
申请号：US13022967
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06F11/1402
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

29. 发明申请

US20120203754A1 PERFORMANCE MONITORING MECHANISM FOR USE IN A PATTERN MATCHING ACCELERATOR 失效
标题翻译：性能监控机制，用于图形匹配加速器
公开(公告)号：US20120203754A1
公开(公告)日：2012-08-09
申请号：US13022904
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30 , G06F13/28
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

30. 发明申请

US20100332798A1 Digital Processor and Method 审中-公开
标题翻译：数字处理器和方法
公开(公告)号：US20100332798A1
公开(公告)日：2010-12-30
申请号：US12825402
申请日：2010-06-29
申请人： Martin Doerr , Hubert Eichner , Markus Kaltenbach , Volker Koch , Ulrich Mayer , Thomas Pflueger , Thomas Schlipf , Cordt Starke , Jan Van Lunteren
发明人： Martin Doerr , Hubert Eichner , Markus Kaltenbach , Volker Koch , Ulrich Mayer , Thomas Pflueger , Thomas Schlipf , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3012 , G06F9/3828 , G06F9/3891
摘要： A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator.
摘要翻译：用于处理数据的处理器的处理器子单元。处理器子单元包括寄存器和用于执行数据指令的至少一个功能单元。寄存器的一个或多个寄存器被连接到至少一个功能单元的输入，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输入。寄存器的一个或多个寄存器被连接到至少一个功能单元的输出，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输出端。至少一个输出总线连接到至少一个寄存器。至少一个输入总线连接到至少一个寄存器。处理器子单元可以用在可以在数据流加速器中使用的处理器中。

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