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21. 发明申请

US20060128126A1 MASKED SIDEWALL IMPLANT FOR IMAGE SENSOR 有权
标题翻译：用于图像传感器的嵌入式平板植入体
公开(公告)号：US20060128126A1
公开(公告)日：2006-06-15
申请号：US10905043
申请日：2004-12-13
申请人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
发明人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
IPC分类号： H01L21/425
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.
摘要翻译：形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离区域。该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

22. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

23. 发明申请

US20070187734A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 失效
标题翻译：具有增强电容的CMOS成像器光电二极管
公开(公告)号：US20070187734A1
公开(公告)日：2007-08-16
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。

24. 发明申请

US20060102939A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 审中-公开
公开(公告)号：US20060102939A1
公开(公告)日：2006-05-18
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

25. 发明申请

US20070184614A1 RECESSED GATE FOR A CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的接收门
公开(公告)号：US20070184614A1
公开(公告)日：2007-08-09
申请号：US11735223
申请日：2007-04-13
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L21/336
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.
摘要翻译：一种新颖的CMOS图像传感器单元结构及其制造方法。成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道收集阱层和扩散区域之间的区域。栅极导体的底部的一部分在衬底的表面下方凹进。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

26. 发明申请

US20070087463A1 PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL 有权
标题翻译：具有分离隔离结构的PIXEL传感器
公开(公告)号：US20070087463A1
公开(公告)日：2007-04-19
申请号：US11563531
申请日：2006-11-27
申请人： James Adkisson , Mark Jaffe , Robert Leidy
发明人： James Adkisson , Mark Jaffe , Robert Leidy
IPC分类号： H01L21/00
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffiusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a comer, or a comer portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离结构。沟槽隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散过程，由此在退火期间，存在于沿着沟槽中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。可替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其拐角部分来减小其尺寸来执行。

27. 发明申请

US20060124976A1 RECESSED GATE FOR AN IMAGE SENSOR 有权
标题翻译：图像传感器的门
公开(公告)号：US20060124976A1
公开(公告)日：2006-06-15
申请号：US10905097
申请日：2004-12-15
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L31/113 , H01L29/76 , H01L29/94
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

28. 发明申请

US20070029581A1 PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元
公开(公告)号：US20070029581A1
公开(公告)日：2007-02-08
申请号：US11161535
申请日：2005-08-08
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L27/148
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明是像素传感器单元及其制造方法。像素传感器单元对于给定的光量大约使可用信号加倍。本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上产生的电子以及形成在基板表面下方的p型收集阱区域用于收集由撞击光子产生的孔。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

29. 发明申请

US20060267013A1 PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL 有权
标题翻译：具有分离隔离结构的PIXEL传感器
公开(公告)号：US20060267013A1
公开(公告)日：2006-11-30
申请号：US10908885
申请日：2005-05-31
申请人： James Adkisson , Mark Jaffe , Robert Leidy
发明人： James Adkisson , Mark Jaffe , Robert Leidy
IPC分类号： H01L29/04 , H01L29/768 , H01L27/148 , H01L29/76
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成隔离结构。隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

30. 发明申请

US20070259500A1 Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method 审中-公开
标题翻译：具有包含氘底物的隔离结构的结构及相关方法
公开(公告)号：US20070259500A1
公开(公告)日：2007-11-08
申请号：US11381861
申请日：2006-05-05
申请人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
发明人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
IPC分类号： H01L21/336 , H01L21/76 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/3003 , H01L21/76283 , H01L21/823481 , H01L29/66772 , H01L29/78 , H01L29/78654
摘要： Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation structure within the substrate, the isolation structure including substantially uniformly distributed deuterium in a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. The substrate may include a semiconductor-on-insulator substrate. A method may include the steps of: providing an isolation structure in a substrate, the isolation structure including deuterium; and annealing to diffuse the deuterium into the substrate (prior to and/or after forming a gate dielectric). The structures and method provide a more efficient means for incorporating deuterium and reducing defects. In addition, the deuterium anneal can occur prior to gate dielectric formation during front-end-of-line processes, such that the anneal temperature can be high to improve deuterium incorporation with reduced anneal time.
摘要翻译：公开了具有包括氘的隔离结构的结构和相关方法。氘优选基本上均匀分布，并且具有大于在天然存在的氢气中发现的浓度（基于总氢原子含量）。一种结构包括用于半导体器件的衬底，该衬底包括衬底内的隔离结构，该隔离结构包括基本上均匀分布的氘，其浓度（基于总氢原子含量）大于在天然存在的氢中发现的浓度。衬底可以包括绝缘体上半导体衬底。一种方法可以包括以下步骤：在衬底中提供隔离结构，所述隔离结构包括氘; 和退火以将氘扩散到衬底中（在形成栅极电介质之前和/或之后）。结构和方法提供了一种更有效的方法来引入氘和减少缺陷。此外，氘退火可以在前端工艺过程中的栅极电介质形成之前发生，使得退火温度可以高以改善氘掺杂并减少退火时间。

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