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1. 发明申请

US20050125711A1 Method and system for defect evaluation using quiescent power plane current (IDDQ) voltage linearity 失效
标题翻译：使用静态功率平面电流（IDDQ）电压线性度进行缺陷评估的方法和系统
公开(公告)号：US20050125711A1
公开(公告)日：2005-06-09
申请号：US10728172
申请日：2003-12-03
申请人： Anne Gattiker , Phillip Nigh
发明人： Anne Gattiker , Phillip Nigh
IPC分类号： G01R31/30 , G06F11/00
CPC分类号： G01R31/3008
摘要： A method and system for defect evaluation using IDDQ voltage linearity provides improved IDDQ testing for determining whether manufacturing defects in a VLSI device are likely to cause functional faults. IDDQ data is collected at multiple power plane voltages (VDDs) for a test vector at which a fault is activated. The IDDQ vs. VDD is then examined and a range of VDDs over which the characteristic IDDQs are non-linear with respect to VDD is determined. Peaks in the first derivative of the IDDQ vs. VDD curve indicate a particular VDD at which the onset of non-linearity in the IDDQ occurs. The VDD point below which the curve is non-linear indicates the relative resistance of a fault with respect to the driving point resistance of the node at which the fault is located. The relative resistance is directly determinative of additional circuit delay cause by the fault and/or whether the fault will cause a logic level transmission failure. Therefore, the range of VDDs for which the IDDQ curve is linear provides a pass/fail indication that can be used to reject devices in manufacturing test.
摘要翻译：使用IDDQ电压线性度进行缺陷评估的方法和系统提供改进的IDDQ测试，用于确定VLSI设备中的制造缺陷是否可能导致功能故障。 IDDQ数据在多个电源平面电压（VDD）下收集，用于启动故障的测试矢量。然后检查IDDQ与VDD，并确定特性IDDQ相对于VDD是非线性的VDD范围。 IDDQ与VDD曲线的一阶导数中的峰值表示IDDQ中发生非线性发生的特定VDD。曲线非线性以下的VDD点表示故障相对于故障位置的节点的驱动点电阻的相对电阻。相对电阻直接决定了故障引起的附加电路延迟和/或故障是否会导致逻辑电平传输故障。因此，IDDQ曲线为线性的VDD的范围提供了可用于在制造测试中拒绝器件的通过/失败指示。

2. 发明授权

US06269461B1 Testing method for dynamic logic keeper device 失效
标题翻译：动态逻辑保护装置的测试方法
公开(公告)号：US06269461B1
公开(公告)日：2001-07-31
申请号：US09067055
申请日：1998-04-27
申请人： Robert Dean Adams , Patrick R. Hansen , Phillip Nigh
发明人： Robert Dean Adams , Patrick R. Hansen , Phillip Nigh
IPC分类号： G01R3128
CPC分类号： G01R31/318525
摘要： A testing device for slowly bleeding charge away from a primary node in a dynamic logic circuit. A properly functioning keeper device in the dynamic logic circuit will maintain the primary node in a precharged state even in the face of this bleeding device. If the logic circuit output flips after the bleeder device begins bleeding charge, a defective keeper device is thereby identified.
摘要翻译：用于在动态逻辑电路中从主节点缓慢渗出电荷的测试装置。动态逻辑电路中正常运行的保持器装置即使面对该出血装置也将使主节点保持在预充电状态。如果逻辑电路输出在泄放装置开始排出电荷之后翻转，从而识别有缺陷的保持装置。

3. 发明申请

US20050289426A1 Functional pattern logic diagnostic method 失效
标题翻译：功能模式逻辑诊断方法
公开(公告)号：US20050289426A1
公开(公告)日：2005-12-29
申请号：US11166019
申请日：2005-06-25
申请人： Donato Forlenza , Franco Molika , Phillip Nigh
发明人： Donato Forlenza , Franco Molika , Phillip Nigh
IPC分类号： G01R31/3185 , G01R31/28 , G06F11/00
CPC分类号： G01R31/318586 , G01R31/318544
摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
摘要翻译：一种诊断半导体器件功能测试故障的方法，通过组合确定性和功能测试，通过确定故障电路中错误类型的位置，基于功能故障创建新的测试模式。这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

4. 发明申请

US20060036975A1 DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US20060036975A1
公开(公告)日：2006-02-16
申请号：US10710879
申请日：2004-08-10
申请人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
发明人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

5. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

6. 发明申请

US20060022693A1 CIRCUIT AND METHOD FOR MONITORING DEFECTS 失效
标题翻译：用于监测缺陷的电路和方法
公开(公告)号：US20060022693A1
公开(公告)日：2006-02-02
申请号：US10710640
申请日：2004-07-27
申请人： Greg Bazan , John Cohn , Matthew Grady , Phillip Nigh , Leah Pastel , Thomas Sopchak
发明人： Greg Bazan , John Cohn , Matthew Grady , Phillip Nigh , Leah Pastel , Thomas Sopchak
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/31855 , H01L2924/0002 , H01L2924/00
摘要： A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.
摘要翻译：用于监测集成电路芯片中的缺陷的电路和方法。所述电路包括缺陷监测部分和感测元件部分，所述缺陷监测部分耦合到布置在链中的感测元件的输入或耦合在感测元件和链的形成部分之间。

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