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1. 发明申请

US20060275978A1 DEEP TRENCH FORMATION IN SEMICONDUCTOR DEVICE FABRICATION 失效
标题翻译：半导体器件制造中的深层形成
公开(公告)号：US20060275978A1
公开(公告)日：2006-12-07
申请号：US11458828
申请日：2006-07-20
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
IPC分类号： H01L21/8242 , H01L29/94 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.
摘要翻译：半导体结构。该结构包括（a）半导体衬底; （b）半导体衬底上的硬掩模层; 和（c）在硬掩模层中开口的硬掩模层。半导体衬底通过硬掩模层开口暴露于大气。硬掩模层开口包括顶部和底部，其中底部设置在顶部和半导体衬底之间。底部具有比顶部更宽的横向宽度。

2. 发明申请

US20060128126A1 MASKED SIDEWALL IMPLANT FOR IMAGE SENSOR 有权
标题翻译：用于图像传感器的嵌入式平板植入体
公开(公告)号：US20060128126A1
公开(公告)日：2006-06-15
申请号：US10905043
申请日：2004-12-13
申请人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
发明人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
IPC分类号： H01L21/425
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.
摘要翻译：形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离区域。该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

3. 发明申请

US20060081556A1 DEEP TRENCH FORMATION IN SEMICONDUCTOR DEVICE FABRICATION 失效
标题翻译：半导体器件制造中的深层形成
公开(公告)号：US20060081556A1
公开(公告)日：2006-04-20
申请号：US10711953
申请日：2004-10-15
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.
摘要翻译：一种用于蚀刻半导体衬底中的深沟槽的方法。该方法包括以下步骤：（a）在半导体衬底的顶部上形成硬掩模层，（b）蚀刻硬掩模层中的硬掩模开口，以通过硬掩模层开口将半导体衬底暴露于大气中其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤，以及（c）蚀刻硬掩模开口的底部的深沟槽基板通过硬掩模开口。

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