专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

2. 发明申请

US20060036975A1 DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US20060036975A1
公开(公告)日：2006-02-16
申请号：US10710879
申请日：2004-08-10
申请人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
发明人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

3. 发明申请

US20050273656A1 LEARNING BASED LOGIC DIAGNOSIS 有权
标题翻译：基于学习的逻辑诊断
公开(公告)号：US20050273656A1
公开(公告)日：2005-12-08
申请号：US10709672
申请日：2004-05-21
申请人： James Adkisson , John Cohn , Leendert Huisman , Maroun Kassab , Leah Pfeifer Pastel , David Sweenor
发明人： James Adkisson , John Cohn , Leendert Huisman , Maroun Kassab , Leah Pfeifer Pastel , David Sweenor
IPC分类号： G06F11/00
CPC分类号： G06F11/2252 , G06F11/261
摘要： A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.
摘要翻译：一种用于诊断电子设备故障的系统和方法。所公开的系统包括：将先前研究的特征与已知故障相关联的缺陷表; 以及故障隔离系统，其将输入的可疑故障设备特征集合与缺陷表中列出的先前研究的特征进行比较，以识别故障原因。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式