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21. 发明授权

US4978594A Fluorine-containing base layer for multi-layer resist processes 失效
标题翻译：含氟基底层用于多层抗蚀剂工艺
公开(公告)号：US4978594A
公开(公告)日：1990-12-18
申请号：US258530
申请日：1988-10-17
申请人： James A. Bruce , Michael L. Kerbaugh , Ranee W. Kwong , Tanya N. Lee , Harold G. Linde , Harbans S. Sachdev
发明人： James A. Bruce , Michael L. Kerbaugh , Ranee W. Kwong , Tanya N. Lee , Harold G. Linde , Harbans S. Sachdev
IPC分类号： H01L21/302 , G03F7/09 , G03F7/40 , H01L21/027 , H01L21/3065
CPC分类号： G03F7/094 , G03F7/405
摘要： A process for forming a pattern on a substrate utilizing photolithographic techniques. In this process a layer of polymeric material containing a fluorine-containing compound is applied over the substrate and cured. A layer of photoresist material is applied over the polymeric material imagewise exposed and developed to reveal the image on the underlying polymeric material. Thereafter, the photoresist is silylated, and the structure is reactive ion etched to transfer the pattern to the underlying substrate. The fluorine component provides an underlying structure free of residue and cracking.

22. 发明授权

US08499260B2 Optical proximity correction verification accounting for mask deviations 失效
标题翻译：光学接近校正验证计算掩模偏差
公开(公告)号：US08499260B2
公开(公告)日：2013-07-30
申请号：US13014159
申请日：2011-01-26
申请人： James A. Bruce , Kenneth T. Settlemyer, Jr.
发明人： James A. Bruce , Kenneth T. Settlemyer, Jr.
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.
摘要翻译：公开了在光学邻近校正验证期间在光刻工艺中考虑光掩模偏差的解决方案。在一个实施例中，一种方法包括：识别表示第一芯片或切口之一的数据集中的晶片控制结构; 在晶片控制结构处于表示第一芯片的数据集的情况下，偏置表示第一芯片的数据组; 在晶片控制结构处于表示切口或第二芯片的数据组的情况下，偏置表示切口的数据组或不同于第一芯片的第二芯片; 模拟晶圆控制结构的形成; 确定模拟晶片控制结构是否符合目标控制结构; 并且在模拟晶片控制结构不符合目标控制结构的情况下，迭代地调整曝光剂量条件。

23. 发明申请

US20120191234A1 DIAGNOSING IN-LINE CRITICAL DIMENSION CONTROL ADJUSTMENTS USING OPTICAL PROXIMITY CORRECTION VERIFICATION 失效
标题翻译：使用光学临近校正验证来诊断在线关键尺寸控制调整
公开(公告)号：US20120191234A1
公开(公告)日：2012-07-26
申请号：US13014152
申请日：2011-01-26
申请人： James A. Bruce , Kenneth T. Settlemyer, JR.
发明人： James A. Bruce , Kenneth T. Settlemyer, JR.
IPC分类号： G06F19/00
CPC分类号： G03F1/36 , G03F1/70 , G03F7/705
摘要： Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.
摘要翻译：公开了用于诊断光刻工艺中的在线临界尺寸控制调整的解决方案。在一个实施例中，一种方法包括：将控制结构定位在表示芯片或切口之一的数据集中; 在靠近控制结构的区域内模拟部件尺寸; 确定区域内的模拟部件尺寸与该区域内的目标部件尺寸之间的差异; 确定所述差异是否超过预定的容差阈值; 响应于确定所述差异来调整模拟条件超过所述预定公差阈值; 并且响应于所述模拟条件的调整，重复所述区域内的所述分量尺寸的模拟，所述差的确定以及所述差是否超过所述预定公差阈值。

24. 发明授权

US08219964B2 Method for creating electrically testable patterns 有权
标题翻译：创建电可测图案的方法
公开(公告)号：US08219964B2
公开(公告)日：2012-07-10
申请号：US12687147
申请日：2010-01-14
申请人： James A. Bruce , Edward W. Conrad , Jacek G. Smolinski
发明人： James A. Bruce , Edward W. Conrad , Jacek G. Smolinski
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36 , G03F1/84 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.
摘要翻译：本发明提供一种用于设计基于从要打印的所需芯片布局导出的图案的电可测图案的方法和计算机程序产品。这种电气测试模式基于围绕关键场所的影响区域内的特征。可以通过例如标记潜在故障位置的OPC验证工具来处理芯片布局来识别关键位置。电测试图案由围绕关键位置的影响区域（ROI）内的特征形成，并且还包括在一个或多个特征的终端处的电馈线，其具有对于印刷环境的变化敏感的电特性关键站点。取决于芯片设计，馈线可以位于与关键位置相同或不同的层上。通过在第二修剪区域内保持特征来进一步限定电气图案，使得ROI内的印刷特征基本上不被第二修剪区域外的特征缺失地修改。

25. 发明授权

US08166423B2 Photomask design verification 失效
标题翻译：光掩模设计验证
公开(公告)号：US08166423B2
公开(公告)日：2012-04-24
申请号：US12555219
申请日：2009-09-08
申请人： Scott M. Mansfield , James A. Bruce , Gregory J. Dick , Ioana Graur
发明人： Scott M. Mansfield , James A. Bruce , Gregory J. Dick , Ioana Graur
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.
摘要翻译：公开了用于验证光掩模设计的解决方案。在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。

26. 发明授权

US07562337B2 OPC verification using auto-windowed regions 失效
标题翻译：使用自动窗口区域进行OPC验证
公开(公告)号：US07562337B2
公开(公告)日：2009-07-14
申请号：US11609033
申请日：2006-12-11
申请人： James A. Bruce , Gregory J. Dick , Donald P. Perley , Jacek G. Smolinski
发明人： James A. Bruce , Gregory J. Dick , Donald P. Perley , Jacek G. Smolinski
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00 , G06K9/00
CPC分类号： G03F1/36
摘要： A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.
摘要翻译：提供了一种用于执行光学邻近校正（“OPC”）验证的方法，其中使用与光掩模的形状，使用光掩模获得的空间图像或光致抗蚀剂图像相关联的数据来识别光掩模的特征使用光掩模在可光成像层中获得。识别光掩模，空中图像或光致抗蚀剂图像的多个区域，其包含所识别的关注特征，其中多个识别区域占据占据特征的光掩模的总面积的面积实质上更小的面积。然后执行限于多个所识别的区域的增强的OPC验证，以识别光掩模，空中图像或光致抗蚀剂图像中的至少一个的问题。

27. 发明授权

US06539321B2 Method for edge bias correction of topography-induced linewidth variation 失效
标题翻译：地形诱导线宽变化的边缘偏置校正方法
公开(公告)号：US06539321B2
公开(公告)日：2003-03-25
申请号：US09906919
申请日：2001-07-17
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold
IPC分类号： G06F1900
CPC分类号： G03F7/70508 , G03F7/70516 , G03F7/70608 , G03F7/70625
摘要： Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.
摘要翻译：用于对用于电子封装的衬底或半导体器件上的印刷或集成电路中遇到的形貌诱导线宽变化的边缘偏置校正的方法。该方法修改了基于先前水平数据和模型的当前水平的数据，关于形貌将影响抗蚀剂和/或抗反射涂层（ARC）厚度的方式，以便改进线宽（LW）控制，一般来说，赋予改进的处理窗口。该方法可以以存储在计算机可用介质上的一个或多个程序模块中体现的计算机可执行指令的形式来实现。

28. 发明授权

US06303416B1 Method to reduce plasma etch fluting 失效
标题翻译：减少等离子体蚀刻凹槽的方法
公开(公告)号：US06303416B1
公开(公告)日：2001-10-16
申请号：US09414457
申请日：1999-10-07
申请人： James A. Bruce , Mary C. Bushey , Premlatha J. Jagannathan , Walter E. Mlyriko , Dianne L. Sundling
发明人： James A. Bruce , Mary C. Bushey , Premlatha J. Jagannathan , Walter E. Mlyriko , Dianne L. Sundling
IPC分类号： H01L2184
CPC分类号： G03F7/38 , G03F7/095 , H01L21/0274 , H01L21/3085 , H01L21/3086 , Y10S438/942
摘要： The present invention is directed to a method and process to reduce plasma etch fluting during etching of a pattern on a semiconductor substrate by modifying the resist profile. The present invention forms a resist structure profile having an overhang or undercut, which is not in contact with the surface of the substrate. The overhang results in a shadowed region on the substrate from the primary etch direction adjacent to the base of the resist structure. Since the overhang is not in direct contact with the substrate surface, the resist pattern does not transfer into the surface of the substrate during etching and fluting is reduced or eliminated.
摘要翻译：本发明涉及一种通过修改抗蚀剂轮廓来在半导体衬底上蚀刻图案期间减少等离子体蚀刻凹槽的方法和方法。本发明形成具有突起或底切的抗蚀剂结构轮廓，其不与基底的表面接触。突出端导致从邻近抗蚀剂结构的基底的主蚀刻方向的衬底上的阴影区域。由于突出部分不与衬底表面直接接触，所以抗蚀剂图案不会在衬底的表面中转移到衬底的表面中蚀刻和凹槽被减少或消除。

29. 发明授权

US06015750A Method for improving visibility of alignment target in semiconductor processing 失效
标题翻译：用于提高半导体处理中的对准目标的可见性的方法
公开(公告)号：US06015750A
公开(公告)日：2000-01-18
申请号：US7694
申请日：1998-01-15
申请人： James A. Bruce , Steven John Holmes , Robert K. Leidy
发明人： James A. Bruce , Steven John Holmes , Robert K. Leidy
IPC分类号： H01L23/544 , G01B11/27
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
摘要翻译：公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。根据第一实施例，在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。根据第二实施例，在金属层上添加反射涂层以增强金属层的反射率。根据第三实施例，在整个晶片上添加反射涂层以增强金属层的反射率。根据第四实施例，添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。根据第五实施例，添加有机抗反射涂层以降低邻近对准靶的材料的反射率。所有这些实施例导致对准目标和相邻材料之间的对比度，其与氧化物厚度的变化更一致。更均匀的对比度使得步进系统更容易识别对准目标的边缘，导致掩模更准确的放置。

30. 发明授权

US5972570A Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby 失效
公开(公告)号：US5972570A
公开(公告)日：1999-10-26
申请号：US895748
申请日：1997-07-17
申请人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
发明人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , G03F7/26
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

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