专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07199624B2 Phase locked loop system capable of deskewing 有权
标题翻译：锁相环系统能够进行偏斜校正
公开(公告)号：US07199624B2
公开(公告)日：2007-04-03
申请号：US10425914
申请日：2003-04-30
申请人： Keng L. Wong , Gregory F. Taylor , Chee How Lim
发明人： Keng L. Wong , Gregory F. Taylor , Chee How Lim
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , G06F1/10 , H03L7/087 , H03L7/235 , H03L2207/04
摘要： A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.
摘要翻译：提供了一种系统，其包括基于参考时钟信号和反馈时钟信号输出第一信号的锁相环组件。时钟分配网络可以基于从锁相环组件输出的第一信号来分配时钟信号。此外，延迟锁定环路分量可能会使信号产生偏斜，并调整由时钟分配网络分配的时钟信号。

22. 发明授权

US06934872B2 Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise 失效
标题翻译：优化时钟分配的方法和装置，以减少电源噪声的影响
公开(公告)号：US06934872B2
公开(公告)日：2005-08-23
申请号：US10021058
申请日：2001-12-19
申请人： Keng L. Wong , Hung-Piao Ma , Tawfik M. Rahal-Arabi , Javed Barkatullah , Edward A. Burton
发明人： Keng L. Wong , Hung-Piao Ma , Tawfik M. Rahal-Arabi , Javed Barkatullah , Edward A. Burton
IPC分类号： G06F1/10 , G06F1/04 , G06F17/50
CPC分类号： G06F1/10
摘要： A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.
摘要翻译：一种用于优化电路中的时钟分布以减少电源噪声的影响的方法和装置。确定参数，包括：电路的电源的响应曲线，到电源的电路中的时钟网络的延迟灵敏度，电路中的数据网到电源的延迟灵敏度，数据延迟数据网和时钟网的时钟延迟。调整时钟延迟以减少电源噪声对数据网的影响。调整是基于电源的响应曲线，时钟网络的延迟灵敏度，数据网络的延迟灵敏度，数据延迟和时钟延迟。调整包括添加预分配时钟延迟。

23. 发明授权

US06885233B2 Altering operating frequency and voltage set point of a circuit in response to the operating temperature and instantaneous operating voltage of the circuit 有权
标题翻译：响应于电路的工作温度和瞬时工作电压，改变电路的工作频率和电压设定点
公开(公告)号：US06885233B2
公开(公告)日：2005-04-26
申请号：US10138345
申请日：2002-05-02
申请人： Douglas Robert Huard , Edward Allyn Burton , Keng L. Wong
发明人： Douglas Robert Huard , Edward Allyn Burton , Keng L. Wong
IPC分类号： G05F1/46 , H01L35/00
CPC分类号： G05F1/46
摘要： Setting the clock frequency provided to a load circuit as function of the operating temperature and supply voltage of the load circuit, and setting the supply voltage as a function of the operating temperature of the load circuit. The load circuit can be safely operated above the frequency which would be the limit if the load circuit were operating at the maximum test temperature. At the given operating temperature, the supply voltage can be raised to permit even higher frequency operation, or lowered to reduce power.
摘要翻译：根据负载电路的工作温度和电源电压设置提供给负载电路的时钟频率，并将电源电压设置为负载电路的工作温度。如果负载电路在最大测试温度下工作，负载电路可以安全地工作在频率以上，这将是极限。在给定的工作温度下，可以提高电源电压以允许甚至更高频率的操作，或降低以降低功率。

24. 发明授权

US06265925B1 Multi-stage techniques for accurate shutoff of circuit 有权
标题翻译：用于电路精确关闭的多级技术
公开(公告)号：US06265925B1
公开(公告)日：2001-07-24
申请号：US09408566
申请日：1999-09-30
申请人： Keng L. Wong , Hung-Piao Ma
发明人： Keng L. Wong , Hung-Piao Ma
IPC分类号： H03L500
CPC分类号： H03K17/693 , H03K17/005
摘要： A multi-stage assembly is disclosed, including a plurality of stages successively arranged, each having a controllable circuit portion and a controlling switching portion coupled thereto. The controlling switching portions have one or more ON/OFF switches which can be MOS transistors, CMOS circuits, etc. A first end of each ON/OFF switch of each controlling switching portion is coupled to a separate node of the controllable circuit portion of that stage and, also, is coupled, respectively, to a second end of a corresponding switch in an adjacent succeeding stage thereby to form selectively actuated one or more strings of series-coupled ON/OFF switches. All switches in an individual string being substantially simultaneously either turned ON or turned OFF. In one such disclosed application, although not limited thereto, the multi-stage assembly features a multi-stage reconfigurable impedance network or, for that matter, a low current/low power biasing network or analog circuit including a cascade arrangement of duplicate circuits in a manner which reduces errors in the output resulting from leakage currents in the turned OFF transistor switches. The number of stages employed, which can be expanded to take into account future scale-downs, also, are based on the level of reduction of subthreshold conduction needed to conform to the error reduction requirements of the circuitry.
摘要翻译：公开了一种多级组件，包括连续布置的多个级，每个级具有可控电路部分和与其耦合的控制切换部分。控制切换部分具有一个或多个可以是MOS晶体管，CMOS电路等的ON / OFF开关。每个控制切换部分的每个ON / OFF开关的第一端耦合到该控制切换部分的可控电路部分的单独节点并且还分别耦合到相邻后级中相应开关的第二端，从而形成选择性地致动的一个或多个串联耦合的开/关开关串。单个字符串中的所有开关基本上同时被接通或关闭。在一个这样公开的应用中，尽管不限于此，多级组件具有多级可重新配置的阻抗网络，或者为此，具有低电流/低功率偏置网络或模拟电路，其包括在减少由断开晶体管开关中的漏电流导致的输出误差的方法。可以扩展以考虑到未来缩减的阶段的数量也是基于减少符合电路的误差降低要求所需的亚阈值传导的程度。

25. 发明授权

US6047383A Multiple internal phase-locked loops for synchronization of chipset components and subsystems operating at different frequencies 失效
标题翻译：用于同步芯片组件和不同频率工作的子系统的多个内部锁相环
公开(公告)号：US6047383A
公开(公告)日：2000-04-04
申请号：US12479
申请日：1998-01-23
申请人： Keith M. Self , Jeffrey E. Smith , Keng L. Wong
发明人： Keith M. Self , Jeffrey E. Smith , Keng L. Wong
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.
摘要翻译：描述了关于在不同频率下需要相对同步性的计算机系统组件和子系统的放置的宽松设计约束的方法和装置。在一个实施例中，该装置包括形成在集成电路管芯上的第一锁相环（PLL）。参考时钟信号引脚通过电长度L1的路径耦合到第一PLL，以将参考时钟信号传播到第一PLL。第一PLL反馈引脚通过电长度L2的路径耦合到第一PLL，其中L1 APPROX L2。该装置包括耦合到参考时钟信号引脚的可编程计数器，该可编程计数器向第一PLL提供划分的基准时钟信号。在一个实施例中，该方法包括向驻留在同一集成电路中的多个PLL提供参考时钟信号的步骤。至少一些PLL的输出耦合到集成电路的相应输出引脚。对于耦合以在传播轨迹结束时提供同步时钟信号的每个选择的输出引脚执行以下步骤：a）确定传播轨迹的电长度; 以及b）提供从所述输出引脚到相应PLL的反馈引脚的反馈迹线，其中所述反馈迹线与所述传播迹线具有相同的电长度。然后，将一个分频参考时钟信号提供给至少一个PLL，其中n不等于1。

26. 发明授权

US5592111A Clock speed limiter for an integrated circuit 失效
标题翻译：集成电路的时钟限速器
公开(公告)号：US5592111A
公开(公告)日：1997-01-07
申请号：US355859
申请日：1994-12-14
申请人： Keng L. Wong , Alexander Waizman , Bart R. McDaniel
发明人： Keng L. Wong , Alexander Waizman , Bart R. McDaniel
IPC分类号： G06F11/00 , G01R23/02 , H03D3/00
CPC分类号： G06F11/0757 , G06F11/076
摘要： A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.
摘要翻译：用于集成电路的调速器，其防止集成电路在选定频率之上的操作。调速器产生频率参考，并将频率参考值与对集成电路进行时钟的外部时钟信号的频率进行比较。作为比较的结果，如果输入时钟信号的频率大于频率参考值，则集成电路的操作被中断。

27. 发明授权

US07408420B2 Multi mode clock generator 有权
标题翻译：多模时钟发生器
公开(公告)号：US07408420B2
公开(公告)日：2008-08-05
申请号：US11237268
申请日：2005-09-27
申请人： Keng L. Wong , Feng Wang
发明人： Keng L. Wong , Feng Wang
IPC分类号： H03L7/00
CPC分类号： G06F1/04
摘要： In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.
摘要翻译：在一些实施例中，提供了提供发生器时钟的时钟发生器。时钟发生器包括提供第一时钟和第二时钟源的第一时钟源，以提供其频率至少间接跟踪到时钟分配网络的电源的第二时钟。当第二个时钟引导第一个时钟时，时钟发生器可选地提供第一个时钟作为发生器时钟，而当第二个时钟滞后于第一个时钟时，时钟发生器可选择地提供第一个时钟。本文要求保护和公开其它实施例。

28. 发明授权

US07310020B2 Self-biased phased-locked loop 有权
公开(公告)号：US07310020B2
公开(公告)日：2007-12-18
申请号：US11321495
申请日：2005-12-29
申请人： Swee Boon Tan , Keng L. Wong
发明人： Swee Boon Tan , Keng L. Wong
IPC分类号： H03L7/00 , H03L7/099
CPC分类号： H03L7/0893 , H03L7/0995 , H03L2207/06
摘要： In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

29. 发明授权

US07242261B2 Voltage control for clock generating circuit 有权
标题翻译：时钟发生电路的电压控制
公开(公告)号：US07242261B2
公开(公告)日：2007-07-10
申请号：US10680498
申请日：2003-10-06
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor
IPC分类号： H03B1/00
CPC分类号： H03K5/15013 , G06F1/10 , G06F1/28 , H03K3/011 , H03K3/0315 , H03K5/133
摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.
摘要翻译：提供了一种装置，其包括时钟分配网络，围绕时钟分配网络设置的多个分布式振荡器，以便在时钟分配网络上提供时钟信号;以及功率控制电路，用于控制施加到多个分布式振荡器的功率。功率控制电路包括用于基于期望功率电平产生参考电压的带隙装置和用于从带隙装置接收参考电压并且从设备外部的源接收电压信号的比较/判定装置。比较/判定装置确定从电源接收的信号是否对应于期望的功率电平。

30. 发明授权

US07197659B2 Global I/O timing adjustment using calibrated delay elements 有权
标题翻译：使用校准延迟元件的全局I / O定时调整
公开(公告)号：US07197659B2
公开(公告)日：2007-03-27
申请号：US09965223
申请日：2001-09-28
申请人： Chee How Lim , Keng L. Wong , Songmin Kim
发明人： Chee How Lim , Keng L. Wong , Songmin Kim
IPC分类号： G06F1/12
CPC分类号： H03L7/0812 , G06F1/10 , H03L7/07
摘要： A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to the received reference clock signal and a feedback clock signal in a phase locked loop. A delay is provided in a path of the reference clock signal and a path of the feedback clock signal. The delay is configured to make the output signal meet a predetermined valid data timing requirement.
摘要翻译：一种方法将信号从发送设备传送到接收设备。使用驱动电路从发送装置输出信号。在发送装置中接收参考时钟信号。根据接收的参考时钟信号和锁相环中的反馈时钟信号产生输出时钟信号。在参考时钟信号的路径和反馈时钟信号的路径中提供延迟。延迟被配置为使输出信号满足预定的有效数据时序要求。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式