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1. 发明授权

US06469533B1 Measuring a characteristic of an integrated circuit 有权
标题翻译：测量集成电路的特性
公开(公告)号：US06469533B1
公开(公告)日：2002-10-22
申请号：US09545922
申请日：2000-04-10
申请人： Nasser A. Kurd , Keng L. Wong , Rachael J. Parker , Hung-Piao Ma
发明人： Nasser A. Kurd , Keng L. Wong , Rachael J. Parker , Hung-Piao Ma
IPC分类号： G01R3102
CPC分类号： G01R31/31926 , G01R31/31905 , G01R31/31915
摘要： An integrated circuit includes a first circuit, a second circuit, at least one test pad and multiplexing circuitry. The second circuit is coupled to the first circuit and has substantially the same design as the first circuit to emulate an electrical characteristic of the first circuit. The multiplexing circuitry selectively couples the test pad(s) to the second circuit to selectively measure the electrical characteristic.
摘要翻译：集成电路包括第一电路，第二电路，至少一个测试焊盘和复用电路。第二电路耦合到第一电路并且具有与第一电路基本相同的设计，以模拟第一电路的电特性。多路复用电路选择性地将测试焊盘耦合到第二电路以选择性地测量电特性。

2. 发明授权

US06407591B1 Self-configurable clock input buffer compatible with high-voltage single-ended and low-voltage differential clock signals 有权
标题翻译：自配置时钟输入缓冲器兼容高压单端和低压差分时钟信号
公开(公告)号：US06407591B1
公开(公告)日：2002-06-18
申请号：US09608238
申请日：2000-06-30
申请人： Keng L. Wong , Hung-Piao Ma , Songmin Kim , Chi-Yeu Chao
发明人： Keng L. Wong , Hung-Piao Ma , Songmin Kim , Chi-Yeu Chao
IPC分类号： H03K522
CPC分类号： G06F1/26 , G06F1/10 , H03K19/018585
摘要： A dual mode clock input buffer is disclosed. The input buffer includes a first portion for handling a single ended high voltage clock signal and a second portion for handling a differential low voltage clock signal.
摘要翻译：公开了一种双模式时钟输入缓冲器。输入缓冲器包括用于处理单端高电压时钟信号的第一部分和用于处理差分低电压时钟信号的第二部分。

3. 发明授权

US07237128B2 Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device 有权
标题翻译：动态地改变电子设备的工作频率和工作电压的方法和装置
公开(公告)号：US07237128B2
公开(公告)日：2007-06-26
申请号：US10855268
申请日：2004-05-26
申请人： Alon Naveh , Roman Surgutchik , Stephen H. Gunther , Robert Greiner , Hung-Piao Ma , Kevin Dai , Keng L. Wong
发明人： Alon Naveh , Roman Surgutchik , Stephen H. Gunther , Robert Greiner , Hung-Piao Ma , Kevin Dai , Keng L. Wong
IPC分类号： G06F1/00 , H03B19/00
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.
摘要翻译：在一个实施例中，提供了一种方法，包括确定电子设备的目标工作点，目标工作点包括目标工作频率和目标工作电压; 以及通过非当前将当前工作频率改变为目标工作频率和当前工作电压到目标工作电压来动态地改变包括当前工作频率和当前工作电压的电子设备的当前工作点，其中在改变期间电子设备处于活动状态。

4. 发明授权

US06934872B2 Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise 失效
标题翻译：优化时钟分配的方法和装置，以减少电源噪声的影响
公开(公告)号：US06934872B2
公开(公告)日：2005-08-23
申请号：US10021058
申请日：2001-12-19
申请人： Keng L. Wong , Hung-Piao Ma , Tawfik M. Rahal-Arabi , Javed Barkatullah , Edward A. Burton
发明人： Keng L. Wong , Hung-Piao Ma , Tawfik M. Rahal-Arabi , Javed Barkatullah , Edward A. Burton
IPC分类号： G06F1/10 , G06F1/04 , G06F17/50
CPC分类号： G06F1/10
摘要： A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.
摘要翻译：一种用于优化电路中的时钟分布以减少电源噪声的影响的方法和装置。确定参数，包括：电路的电源的响应曲线，到电源的电路中的时钟网络的延迟灵敏度，电路中的数据网到电源的延迟灵敏度，数据延迟数据网和时钟网的时钟延迟。调整时钟延迟以减少电源噪声对数据网的影响。调整是基于电源的响应曲线，时钟网络的延迟灵敏度，数据网络的延迟灵敏度，数据延迟和时钟延迟。调整包括添加预分配时钟延迟。

5. 发明授权

US06265925B1 Multi-stage techniques for accurate shutoff of circuit 有权
标题翻译：用于电路精确关闭的多级技术
公开(公告)号：US06265925B1
公开(公告)日：2001-07-24
申请号：US09408566
申请日：1999-09-30
申请人： Keng L. Wong , Hung-Piao Ma
发明人： Keng L. Wong , Hung-Piao Ma
IPC分类号： H03L500
CPC分类号： H03K17/693 , H03K17/005
摘要： A multi-stage assembly is disclosed, including a plurality of stages successively arranged, each having a controllable circuit portion and a controlling switching portion coupled thereto. The controlling switching portions have one or more ON/OFF switches which can be MOS transistors, CMOS circuits, etc. A first end of each ON/OFF switch of each controlling switching portion is coupled to a separate node of the controllable circuit portion of that stage and, also, is coupled, respectively, to a second end of a corresponding switch in an adjacent succeeding stage thereby to form selectively actuated one or more strings of series-coupled ON/OFF switches. All switches in an individual string being substantially simultaneously either turned ON or turned OFF. In one such disclosed application, although not limited thereto, the multi-stage assembly features a multi-stage reconfigurable impedance network or, for that matter, a low current/low power biasing network or analog circuit including a cascade arrangement of duplicate circuits in a manner which reduces errors in the output resulting from leakage currents in the turned OFF transistor switches. The number of stages employed, which can be expanded to take into account future scale-downs, also, are based on the level of reduction of subthreshold conduction needed to conform to the error reduction requirements of the circuitry.
摘要翻译：公开了一种多级组件，包括连续布置的多个级，每个级具有可控电路部分和与其耦合的控制切换部分。控制切换部分具有一个或多个可以是MOS晶体管，CMOS电路等的ON / OFF开关。每个控制切换部分的每个ON / OFF开关的第一端耦合到该控制切换部分的可控电路部分的单独节点并且还分别耦合到相邻后级中相应开关的第二端，从而形成选择性地致动的一个或多个串联耦合的开/关开关串。单个字符串中的所有开关基本上同时被接通或关闭。在一个这样公开的应用中，尽管不限于此，多级组件具有多级可重新配置的阻抗网络，或者为此，具有低电流/低功率偏置网络或模拟电路，其包括在减少由断开晶体管开关中的漏电流导致的输出误差的方法。可以扩展以考虑到未来缩减的阶段的数量也是基于减少符合电路的误差降低要求所需的亚阈值传导的程度。

6. 发明授权

US06208169B1 Internal clock jitter detector 有权
标题翻译：内部时钟抖动检测器
公开(公告)号：US06208169B1
公开(公告)日：2001-03-27
申请号：US09340975
申请日：1999-06-28
申请人： Keng L. Wong , Gregory F. Taylor , Ravishankar Kuppuswamy , Douglas R. Parker , Hung-Piao Ma , Kent R. Callahan , Xia Dai
发明人： Keng L. Wong , Gregory F. Taylor , Ravishankar Kuppuswamy , Douglas R. Parker , Hung-Piao Ma , Kent R. Callahan , Xia Dai
IPC分类号： H03K19096
CPC分类号： H03L7/091 , H03L7/0814
摘要： An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.
摘要翻译：公开了一种用于检测和测量内部时钟抖动的装置和方法。在一个实施例中，参考时钟发生器基于瞬时时钟信号产生参考时钟信号。参考时钟信号包括延迟平均持续时间的瞬时时钟信号。相位比较元件接收瞬时时钟信号和参考时钟信号，使得相位比较元件测量瞬时时钟信号和参考时钟信号之间的相位差。相位差的幅度和方向由相位比较元件中的多个不同的相位差区之一表示。

7. 发明申请

US20060156040A1 Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device 有权
公开(公告)号：US20060156040A1
公开(公告)日：2006-07-13
申请号：US10855268
申请日：2004-05-26
申请人： Alon Naveh , Roman Surgutchik , Stephen Gunther , Robert Greiner , Hung-Piao Ma , Kevin Dai , Keng Wong
发明人： Alon Naveh , Roman Surgutchik , Stephen Gunther , Robert Greiner , Hung-Piao Ma , Kevin Dai , Keng Wong
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

8. 发明申请

US20060052970A1 On-die temperature control data for communicating to a thermal actuator 有权
公开(公告)号：US20060052970A1
公开(公告)日：2006-03-09
申请号：US10924719
申请日：2004-08-23
申请人： Tawfik Arabi , Hung-Piao Ma , Benson Inkley , Gregory Iovino , Stephen Gunther , Matthew Reilly
发明人： Tawfik Arabi , Hung-Piao Ma , Benson Inkley , Gregory Iovino , Stephen Gunther , Matthew Reilly
IPC分类号： G01K1/08 , G06F15/00
CPC分类号： G06F1/206
摘要： An on-die temperature control variable is provided to throttle a thermal actuator for cooling an integrated circuit. The integrated circuit includes a storage element to hold the temperature control variable. A temperature sensor is thermally coupled to the integrated circuit to sense an operating temperature of the integrated circuit. A thermal controller is communicatively coupled to the storage element and to the temperature sensor. The thermal controller throttles the thermal actuator when the temperature sensor indicates that the operating temperature of the integrated circuit is below the temperature control variable.

9. 发明授权

US08508073B2 Simultaneous multi-voltage rail voltage regulation messages 有权
标题翻译：同时多电压轨电压调节信号
公开(公告)号：US08508073B2
公开(公告)日：2013-08-13
申请号：US13551481
申请日：2012-07-17
申请人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Pedro Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
发明人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Pedro Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
IPC分类号： H02J1/00
CPC分类号： H02J1/10 , G11C5/147 , H02J2001/008 , Y10T307/305 , Y10T307/658 , Y10T307/675
摘要： Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.
摘要翻译：同时调节通过电压调节器提供给集成电路的两个或多个电源电压的方法和机制。在本发明的一个实施例中，在集成电路和电压调节器之间交换的电压调节消息包括一个标识符，该标识符指示通过电压调节器从提供给集成电路的多个电源电压中选择的两个或多个电源电压，其中电压调节消息涉及所指示的两个或更多个电源电压。在另一个实施例中，电压调节消息指示所指示的两个或更多个电源电压要转换到的期望电源电压电平。

10. 发明授权

US08222766B2 Simultaneous multi-voltage rail voltage regulation messages 有权
标题翻译：同时多电压轨电压调节信号
公开(公告)号：US08222766B2
公开(公告)日：2012-07-17
申请号：US13094599
申请日：2011-04-26
申请人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
发明人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
IPC分类号： H02J1/00
CPC分类号： H02J1/10 , G11C5/147 , H02J2001/008 , Y10T307/305 , Y10T307/658 , Y10T307/675
摘要： Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.
摘要翻译：同时调节通过电压调节器提供给集成电路的两个或多个电源电压的方法和机制。在本发明的一个实施例中，在集成电路和电压调节器之间交换的电压调节消息包括一个标识符，该标识符指示通过电压调节器从提供给集成电路的多个电源电压中选择的两个或多个电源电压，其中电压调节消息涉及所指示的两个或更多个电源电压。在另一个实施例中，电压调节消息指示所指示的两个或更多个电源电压要转换到的期望电源电压电平。

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