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21. 发明授权

US09172373B2 Verifying partial good voltage island structures 有权
标题翻译：验证部分良好电压岛结构
公开(公告)号：US09172373B2
公开(公告)日：2015-10-27
申请号：US14019957
申请日：2013-09-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin W. Gorman , Steven F. Oakland , Michael R. Ouellette , Steven J. Urish
IPC分类号： H03K19/003 , G06F17/50 , G06F1/32
CPC分类号： H03K19/00392 , G06F1/3287 , G06F17/505 , G06F2217/72 , G06F2217/78
摘要： Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.
摘要翻译：提供了用于设计和验证集成电路（包括冗余逻辑块）的结构，方法和系统。集成电路包括由选择逻辑单独控制的选择逻辑和可选逻辑块。可选逻辑块包括冗余逻辑块的相应实例，以及选择性地禁用集成电路中的冗余逻辑块的接口逻辑块的相应实例。

22. 发明授权

US08935586B2 Staggered start of BIST controllers and BIST engines 有权
标题翻译： BIST控制器和BIST引擎交错启动
公开(公告)号：US08935586B2
公开(公告)日：2015-01-13
申请号：US13671605
申请日：2012-11-08
申请人： International Business Machines Corporation
发明人： Valarie H. Chickanosky , Kevin W. Gorman , Suzanne Granato , Michael R. Ouellette , Nancy H. Pratt , Michael A. Ziegerhofer
IPC分类号： G01R31/28
CPC分类号： G01R31/31724
摘要： Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.
摘要翻译：每个内置自检（BIST）控制器中的每个寄存器包含与至少一个其他BIST控制器特定启动计数不同的BIST控制器特定的起始计数值。测试控制器同时向所有BIST控制器提供启动命令。这使得每个BIST控制器使用计数器同时开始BIST控制器特定的开始计数值的倒计时。每个BIST控制器在倒计时完成时（在相应的BIST控制器中），在对应的BIST域中启动测试过程。因此，根据不同寄存器中BIST控制器特定的开始计数值的差异，测试过程在至少两个BIST域中的不同时间开始。此外，在测试过程中，每个交错控制器可以错开交错控制器所连接的相应BIST域内的每个BIST引擎的开始。

23. 发明授权

US10692584B2 Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register 有权
公开(公告)号：US10692584B2
公开(公告)日：2020-06-23
申请号：US15801444
申请日：2017-11-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. Busi , John R. Goss , Paul J. Grzymkowski , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/38 , G11C29/44 , G11C29/40 , G11C29/56 , G11C29/00 , G11C29/36
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

24. 发明授权

US09773570B2 Built-in-self-test (BIST) test time reduction 有权
公开(公告)号：US09773570B2
公开(公告)日：2017-09-26
申请号：US13786572
申请日：2013-03-06
申请人： International Business Machines Corporation
发明人： Kevin W. Gorman , Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G11C29/40 , G01R31/317 , G01R31/3185
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/318547
摘要： Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

25. 发明授权

US09734920B2 Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories 有权
公开(公告)号：US09734920B2
公开(公告)日：2017-08-15
申请号：US14867299
申请日：2015-09-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin W. Gorman , Michael R. Ouellette , Patrick E. Perry
IPC分类号： G11C29/42 , G11C29/36 , G11C29/44 , G11B20/18 , G11C29/12
CPC分类号： G11C29/42 , G11B20/182 , G11C29/12 , G11C29/36 , G11C29/44 , G11C29/4401 , G11C2029/3602
摘要： Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

26. 发明申请

US20160365156A1 BUILT-IN SELF-TEST (BIST) CIRCUIT AND ASSOCIATED BIST METHOD FOR EMBEDDED MEMORIES 有权
标题翻译：用于嵌入式存储器的内置自检（BIST）电路和相关的BIST方法
公开(公告)号：US20160365156A1
公开(公告)日：2016-12-15
申请号：US14734041
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： Aravindan J. Busi , Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G11C29/18 , G11C29/38 , G11C29/36
CPC分类号： G11C29/18 , G11C29/36 , G11C29/38
摘要： Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.
摘要翻译：公开了一种具有内置自检（BIST）电路的芯片，其包含并行测试存储器的BIST引擎，并且在测试之前动态地设置要扫描的地址空间的大小。 BIST引擎包括地址发生器，其确定与所有存储器相关联的地址空间值的超集。该超集表示最高数量的存储体，每个存储体的字数最多，并且任何存储器的解码数量最高。然后，地址生成器生成测试地址并且这样做，使得所有测试地址在由超集合定义的复合地址空间内，并且因此在可能根据存储器配置的地址空间内小于相关联的预定最大地址空间具有这样的记忆，以减少测试时间。还公开了一种用于测试存储器的相关联的BIST方法。

27. 发明授权

US08918690B2 Decreasing power supply demand during BIST initializations 有权
标题翻译： BIST初始化期间电力需求下降
公开(公告)号：US08918690B2
公开(公告)日：2014-12-23
申请号：US13732711
申请日：2013-01-02
申请人： International Business Machines Corporation
发明人： Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G01R31/28 , G11C29/12
CPC分类号： G11C29/12015 , G11C29/12005 , G11C29/16 , G11C29/26 , G11C2029/2602
摘要： Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.
摘要翻译：本发明的方面提供了在内置自检（BIST）初始化期间降低供电需求。在一个实施例中，用于在BIST初始化期间减少电源需求的BIST架构包括：一系列缓慢的BIST I / O接口; 一连串快速BIST I / O接口，每个快速BIST I / O接口连接到一个缓慢的BIST I / O接口; 以及BIST引擎，其包括用于控制每个慢BIST I / O接口内的复用器的突发交错锁存器，其中针对第一突发信号的脉冲串交错锁存器将第一突发信号交错到每个慢BIST I / O 接口，使得在第一时钟周期期间，仅第一慢BIST I / O接口接收第一个突发信号。

28. 发明授权

US08914688B2 System and method of reducing test time via address aware BIST circuitry 有权
标题翻译：通过地址感知BIST电路减少测试时间的系统和方法
公开(公告)号：US08914688B2
公开(公告)日：2014-12-16
申请号：US13685779
申请日：2012-11-27
申请人： International Business Machines Corporation
发明人： George M. Belansek , Kevin W. Gorman , Kiran K. Narayan , Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G11C29/00 , G11C29/20
CPC分类号： G11C29/20
摘要： In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.
摘要翻译：在具有公共BIST控制单元的IC存储器阵列上执行BIST操作的方法中，启动第一BIST序列。数组的每个地址递增。 BIST控制单元接收指示到达阵列中的最大有效地址的信号，接收被记录的多个最大有效地址。确定单个相对较高的最大有效地址。阻止BIST测试的第一种模式是在达到最大有效地址的每个阵列中进行操作。基于已经接收到指示从连接到公共BIST控制单元的所有阵列到达最大有效地址的信号，启动第二BIST序列。地址计数从单个相对较高的最大有效地址递减。由于地址计数在递减期间达到每个最大有效地址，所以每个阵列的第一个模式被分离。

29. 发明申请

US20140258797A1 BUILT-IN-SELF-TEST (BIST) TEST TIME REDUCTION 有权
标题翻译：内置自检（BIST）测试时间缩短
公开(公告)号：US20140258797A1
公开(公告)日：2014-09-11
申请号：US13786572
申请日：2013-03-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin W. Gorman , Deepak I. Hanagandi , Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G11C29/40
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/318547
摘要： Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.
摘要翻译：本发明的方面提供减少IC芯片的存储器的BIST测试时间。在一个实施例中，一种用于减少用于集成电路（IC）芯片的存储器的BIST测试时间的BIST架构，该架构包括：一对锁存器，用于从存储器接收数据; 第一压缩级，用于接收数据的脉冲串并将数据的脉冲串压缩成多个锁存器; 用于将压缩的数据突发与预期数据进行比较的第二压缩级; 以及用于确定数据突发是否存在故障的逻辑门。

30. 发明授权

US08612813B2 Circuit and method for efficient memory repair 有权
标题翻译：电路和方法进行高效的内存修复
公开(公告)号：US08612813B2
公开(公告)日：2013-12-17
申请号：US13750497
申请日：2013-01-25
申请人： International Business Machines Corporation
发明人： Valerie H. Chickanosky , Kevin W. Gorman , Suzanne Granato , Michael R. Ouellette
IPC分类号： G06F11/00 , G01R31/28 , G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0401
摘要： A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
摘要翻译：一种用于测试存储器并为给定地址位置计算修复解决方案的电路和方法包括：在检测集成电路的故障存储器输出数据时暂停内置自检（BIST）操作。在暂停期间，电路和方法使用分析逻辑在“n”个周期期间分析“n”个故障存储器输出数据组，并计算修复解决方案。正常操作可以恢复。

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