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21. 发明申请

US20070022250A1 System and method of responding to a cache read error with a temporary cache directory column delete 审中-公开
标题翻译：使用临时缓存目录列删除缓存读取错误的系统和方法
公开(公告)号：US20070022250A1
公开(公告)日：2007-01-25
申请号：US11184343
申请日：2005-07-19
申请人： James Fields , Guy Guthrie , William Starke , Phillip Williams
发明人： James Fields , Guy Guthrie , William Starke , Phillip Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/126 , G06F2212/1032
摘要： A system and method of responding to a cache read error with a temporary cache directory column delete. A read command is received at a cache controller. In response to determining that data requested by said read command is stored in a specific data location in the cache, a read of the data is initiated. In response to determining the read of said data results in an error, a column delete indicator for an associativity class including a specific data location to temporarily prevent allocation within the associativity class of storage locations is set. A specific line delete command that marks the specific data location as deleted is issued. In response to the issuing of the specific line delete command, the column delete indicator for the associativity class, such that storage locations within the associativity class other than the specific data location can again be allocated to hold new data is set.
摘要翻译：使用临时高速缓存目录列删除来响应缓存读取错误的系统和方法。在高速缓存控制器处接收读命令。响应于确定由所述读取命令请求的数据被存储在高速缓存中的特定数据位置中，开始读取数据。响应于确定所述数据的读取导致错误，设置用于包括特定数据位置的关联性类的列删除指示符，以临时阻止存储位置的关联性类别内的分配。发出将特定数据位置标记为已删除的特定行删除命令。响应于发出特定行删除命令，设置关联性类的列删除指示符，使得可以再次分配除特定数据位置之外的关联性类中的存储位置以保存新数据。

22. 发明申请

US20060179253A1 Data processing system, method and interconnect fabric that protect ownership transfer with a protection window extension 审中-公开
标题翻译：数据处理系统，方法和互连结构，通过保护窗口扩展来保护所有权转移
公开(公告)号：US20060179253A1
公开(公告)日：2006-08-10
申请号：US11054841
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016 , G06F2212/1048
摘要： A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to the partial responses provided by the plurality of snoopers. The plurality masters includes a winning master that issues a request for a particular memory block, and the plurality of snoopers includes a protecting snooper that, in response to receipt of the request, provides a partial response and protects a transfer of coherency ownership of the particular memory block to the winning master until expiration of a protection window extension following receipt from the response logic of a combined response for the request.
摘要翻译：数据处理系统包括存储器系统，发出对存储器系统内的存储器块的访问请求的多个主器件，提供对由主器件发出的请求的部分响应的多个监视器以及产生针对请求的组合响应的响应逻辑响应于由多个窥探者提供的部分响应。多个主人包括发出对特定存储块的请求的获胜主，并且多个窥探者包括保护窥探者，其响应于该请求的接收而提供部分响应并保护特定存储块的一致性所有权的转移记忆块到获胜主机，直到从请求的组合响应的响应逻辑接收到保护窗口扩展之后到期。

23. 发明申请

US20060179230A1 Half-good mode for large L2 cache array topology with different latency domains 有权
标题翻译：具有不同延迟域的大型L2缓存阵列拓扑的半好模式
公开(公告)号：US20060179230A1
公开(公告)日：2006-08-10
申请号：US11055262
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , Kirk Livingston , William Starke
发明人： James Fields , Guy Guthrie , Kirk Livingston , William Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/126
摘要： A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is part of a first cache line in the first cache slice and part of a second cache line in the second cache slice, it is disabled while continuing to use at least one other cache way which is also part of the first cache line and part of the second cache line. In the illustrative embodiment the cache array is set associative and at least two different cache ways for a given cache line contain different congruence classes for that cache line. The defective cache way can be disabled by preventing an eviction mechanism from allocating any congruence class in the defective way. For example, half of the cache line can be disabled (i.e., half of the congruence classes). The cache array may be arranged with rows and columns of cache sectors (rows corresponding to the cache ways) wherein a given cache line is further spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array can also output different sectors of the given cache line in successive clock cycles based on the latency of a given sector.
摘要翻译：高速缓存存储器将高速缓存阵列逻辑地分区成至少两个切片，每个切片具有多个高速缓存行，其中给定的高速缓存行分布在连续字节的两个或多个高速缓存路径上以及在两个高速缓存片之间共享的给定高速缓存路径，如果一个缓存方式是缺陷，其是第一高速缓存片中的第一高速缓存行和第二高速缓存片中的第二高速缓存行的一部分的一部分，其被禁用，同时继续使用至少一种其他高速缓存方式，其也是第一个缓存行和第二个缓存行的一部分。在说明性实施例中，高速缓存阵列被设置为关联性，并且给定高速缓存行的至少两个不同的高速缓存路径包含该高速缓存行的不同的一致类。可以通过防止驱逐机制以有缺陷的方式分配任何一致类来禁用缺陷缓存方式。例如，可以禁用一半的高速缓存行（即，一致等级的一半）。高速缓存阵列可以被布置成具有行和列的高速缓存扇区（对应于高速缓存路线的行），其中给定高速缓存行进一步分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一延迟的第一列和给定高速缓存行的另一部分位于具有大于第一等待时间的第二等待时间的第二列中。缓存阵列还可以基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。

24. 发明申请

US20060179229A1 L2 cache controller with slice directory and unified cache structure 失效
公开(公告)号：US20060179229A1
公开(公告)日：2006-08-10
申请号：US11054924
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/0811
摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry. The cache array may be arranged with rows and columns of cache sectors wherein a given cache line is spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array outputs different sectors of the given cache line in successive clock cycles based on the latency of a given sector.

25. 发明申请

US20080028156A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT STORAGE OF METADATA IN A SYSTEM MEMORY 有权
标题翻译：数据处理系统和方法，用于在系统存储器中有效存储元数据
公开(公告)号：US20080028156A1
公开(公告)日：2008-01-31
申请号：US11836908
申请日：2007-08-10
申请人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
发明人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

26. 发明申请

US20060179248A1 Data processing system and method for efficient storage of metadata in a system memory 失效
标题翻译：用于在系统存储器中有效存储元数据的数据处理系统和方法
公开(公告)号：US20060179248A1
公开(公告)日：2006-08-10
申请号：US11055640
申请日：2005-02-10
申请人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
发明人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

27. 发明申请

US20070088926A1 Data processing system and method in which a participant initiating a read operation protects data integrity 失效
标题翻译：数据处理系统和方法，其中发起读取操作的参与者保护数据完整性
公开(公告)号：US20070088926A1
公开(公告)日：2007-04-19
申请号：US11250022
申请日：2005-10-13
申请人： James Fields , Guy Guthrie , John Hollaway , Derek Williams
发明人： James Fields , Guy Guthrie , John Hollaway , Derek Williams
IPC分类号： G06F12/14
CPC分类号： G06F12/0831 , G06F12/0815 , G06F12/0824
摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.
摘要翻译：数据处理系统包括多个请求者和用于系统存储器的存储器控制器。响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示存储器控制器将该存储器块发送给请求者。在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

28. 发明申请

US20050071573A1 Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes 失效
标题翻译：修改的无效缓存状态，以减少用于推测发出的全缓存行写入的缓存到高速缓存数据传输操作
公开(公告)号：US20050071573A1
公开(公告)日：2005-03-31
申请号：US10675744
申请日：2003-09-30
申请人： John Dodson , James Fields , Guy Guthrie , Kenneth Wright
发明人： John Dodson , James Fields , Guy Guthrie , Kenneth Wright
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0835 , G06F12/0831 , G06F2212/507
摘要： A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.
摘要翻译：包括经修改的无效（Mi）状态的高速缓存一致性协议，其使得能够执行DMA声明或DClaim操作以将高速缓存行的唯一所有权分配给要覆盖整个高速缓存行的设备，而不进行高速缓存 - 缓存数据传输。该协议允许完成推测发出的完整高速缓存行写入，而不需要在先前的DMA声明或DClaim操作期间在数据总线上缓存到高速缓存传输数据。修改无效（Mi）状态将高速缓存行的唯一所有权分配给推测性地发出DMA写入的I / O设备或者推测发出DCBZ操作以覆盖整个高速缓存行的处理器，并且将Mi 状态可防止将数据从另一个缓存发送到高速缓存行，因为数据最有可能被覆盖。

29. 发明申请

US20060179252A1 Data processing system and method for efficient communication utilizing an In coherency state 有权
标题翻译：数据处理系统和利用一致性状态的高效通信方法
公开(公告)号：US20060179252A1
公开(公告)日：2006-08-10
申请号：US11055305
申请日：2005-02-10
申请人： Jason Cantin , James Fields , Steven Kunkel , William Starke
发明人： Jason Cantin , James Fields , Steven Kunkel , William Starke
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

30. 发明申请

US20060190636A1 Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations 失效
标题翻译：在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置
公开(公告)号：US20060190636A1
公开(公告)日：2006-08-24
申请号：US11054183
申请日：2005-02-09
申请人： George Daly , James Fields
发明人： George Daly , James Fields
IPC分类号： G06F13/28
CPC分类号： G06F12/0835 , G06F13/28
摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.
摘要翻译：公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。最初，外围设备发出多高速缓存行DMA请求。多高速缓存行DMA请求被缓存内存窥探。然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。

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