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1. 发明申请

US20070088926A1 Data processing system and method in which a participant initiating a read operation protects data integrity 失效
标题翻译：数据处理系统和方法，其中发起读取操作的参与者保护数据完整性
公开(公告)号：US20070088926A1
公开(公告)日：2007-04-19
申请号：US11250022
申请日：2005-10-13
申请人： James Fields , Guy Guthrie , John Hollaway , Derek Williams
发明人： James Fields , Guy Guthrie , John Hollaway , Derek Williams
IPC分类号： G06F12/14
CPC分类号： G06F12/0831 , G06F12/0815 , G06F12/0824
摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.
摘要翻译：数据处理系统包括多个请求者和用于系统存储器的存储器控制器。响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示存储器控制器将该存储器块发送给请求者。在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

2. 发明申请

US20070180196A1 Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains 失效
标题翻译：数据处理系统，缓存系统和用于处理具有多个相干域的数据处理系统中的刷新操作的方法
公开(公告)号：US20070180196A1
公开(公告)日：2007-08-02
申请号：US11342951
申请日：2006-01-30
申请人： Guy Guthrie , John Hollaway , William Starke , Derek Williams
发明人： Guy Guthrie , John Hollaway , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0804 , G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。第一相干域包括存储器控制器，具有由目标地址标识的目标存储器块的相关系统存储器，以及指示目标存储器块是否被高速缓存在第一相干域之外的域指示符。在操作期间，第一相干域接收向第一和第二相干域广播的刷新操作，其中刷新操作指定目标存储器块的目标地址。第一个相干域还接收表示对刷新操作的系统范围响应的刷新操作的组合响应。响应于在组合响应的第一相关域中的接收，确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。响应于组合响应指示目标存储器块的高速缓存副本可能保留在数据处理系统中的确定，更新域指示符以指示目标存储器块被高速缓存在第一相干域之外。

3. 发明申请

US20060179242A1 Data processing system and method for handling castout collisions 有权
标题翻译：数据处理系统及其处理方法
公开(公告)号：US20060179242A1
公开(公告)日：2006-08-10
申请号：US11054888
申请日：2005-02-10
申请人： Sanjeev Ghai , Guy Guthrie , John Hollaway
发明人： Sanjeev Ghai , Guy Guthrie , John Hollaway
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.
摘要翻译：数据处理系统包括系统存储器的存储器控制器，其接收指定相同地址的第一和第二突变操作。响应于接收到所述第一和第二停顿操作，存储器控制器对系统存储器执行单次更新。

4. 发明申请

US20080040557A1 DATA PROCESSING SYSTEM AND METHOD FOR HANDLING CASTOUT COLLISIONS 有权
标题翻译：数据处理系统和处理CASTOUT冲突的方法
公开(公告)号：US20080040557A1
公开(公告)日：2008-02-14
申请号：US11836207
申请日：2007-08-09
申请人： Sanjeev Ghai , Guy Guthrie , John Hollaway
发明人： Sanjeev Ghai , Guy Guthrie , John Hollaway
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.
摘要翻译：数据处理系统包括系统存储器的存储器控制器，其接收指定相同地址的第一和第二突变操作。响应于接收到所述第一和第二停顿操作，存储器控制器对系统存储器执行单次更新。

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