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1. 发明申请

US20070143511A1 Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效
标题翻译：用于将计算系统的组件与一对单向点对点总线接口的方法和系统
公开(公告)号：US20070143511A1
公开(公告)日：2007-06-21
申请号：US11304474
申请日：2005-12-15
申请人： George Daly , James Fields , Donald Grice , Thomas Heller , Appoloniel Tankeh
发明人： George Daly , James Fields , Donald Grice , Thomas Heller , Appoloniel Tankeh
IPC分类号： G06F13/00
CPC分类号： G06F13/4269
摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.
摘要翻译：提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据，计算系统。该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。该方法还包括提供用于在从总线控制器接收到命令分组之后从属总线控制器接收到用于命令分组的第一信令间隔的从总线控制器向主总线控制器发送确认的装置。

2. 发明申请

US20060179185A1 Method to preserve ordering of read and write operations in a DMA system by delaying read access 有权
标题翻译：通过延迟读访问来保持DMA系统中读写操作顺序的方法
公开(公告)号：US20060179185A1
公开(公告)日：2006-08-10
申请号：US11054403
申请日：2005-02-09
申请人： George Daly , James Fields , Paul Umbarger , Kenneth Wright
发明人： George Daly , James Fields , Paul Umbarger , Kenneth Wright
IPC分类号： G06F3/06
CPC分类号： G06F13/28 , G06F12/0815 , G06F12/0897
摘要： A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.
摘要翻译：公开了一种用于在数据处理系统中处理写入请求的方法，系统和计算机程序产品。该方法包括在互连总线上接收针对第一地址的第一写入请求，并且在互连总线上接收针对随后的第二地址的后续的第二写入请求。随后的第二写请求在完成第一写请求之前完成，并且响应于在第一写请求完成之前接收到针对第二地址的读请求，与第二写请求的第二地址相关联的数据仅在第一个写请求完成。

3. 发明申请

US20060190685A1 Method and apparatus for invalidating entries within a translation control entry (TCE) cache 有权
标题翻译：用于使翻译控制条目（TCE）高速缓存中的条目无效的方法和装置
公开(公告)号：US20060190685A1
公开(公告)日：2006-08-24
申请号：US11054182
申请日：2005-02-09
申请人： Richard Arndt , George Daly , James Fields , Warren Maule
发明人： Richard Arndt , George Daly , James Fields , Warren Maule
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F12/0837 , G06F12/084 , G06F12/1081 , G06F2212/1041 , G06F2212/683
摘要： A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.
摘要翻译：公开了一种使翻译控制条目（TCE）高速缓存内的条目无效的方法和装置。主机桥耦合在一组处理器和一组适配器之间。主机桥包括TCE缓存。 TCE缓存包含位于系统内存中的TCE表中最近使用的TCE的副本。响应于一个处理器对TCE表中的TCE进行修改，将存储器映射的输入/输出（MMIO）存储发送到TCE无效寄存器，以指定修改的TCE的地址。然后使用TCE无效寄存器内的数据来产生用于使包含TCE表中修改的TCE的未修改副本的TCE缓存中的条目无效的命令。该命令随后发送到主机桥，使TCE缓存中的条目无效。

4. 发明授权

US5719508A Loss of lock detector for master timing generator 失效
标题翻译：主定时发生器的锁定检测器丢失
公开(公告)号：US5719508A
公开(公告)日：1998-02-17
申请号：US595583
申请日：1996-02-01
申请人： William George Daly
发明人： William George Daly
IPC分类号： H03L7/095 , H03L7/097 , H03D3/24
CPC分类号： H03L7/095 , Y10S331/02
摘要： A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.
摘要翻译：用于相位环路（PLL）的锁定检测（LLD）设备的数字丢失产生与参考频率信号同步的锁定频率信号。 LLD包括第一至第五锁存装置，用于当锁定的时钟失败高/低时以及当基准时钟在PLL的跟踪范围之外时检测参考时钟何时失败高/低。第一至第五锁存装置分别为每种类型的上述故障提供第一至第五误差信号。

5. 发明申请

US20070300000A1 METHOD FOR INTERFACING COMPONENTS OF A COMPUTING SYSTEM WITH A PAIR OF UNIDIRECTIONAL, POINT-TO-POINT BUSES 失效
标题翻译：用于将计算机系统的组件与一对单向点对点总线接口的方法
公开(公告)号：US20070300000A1
公开(公告)日：2007-12-27
申请号：US11854004
申请日：2007-09-12
申请人： George DALY , James FIELDS , Donald GRICE , Thomas HELLER , Appoloniel TANKEH
发明人： George DALY , James FIELDS , Donald GRICE , Thomas HELLER , Appoloniel TANKEH
IPC分类号： G06F13/00
CPC分类号： G06F13/4269
摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.
摘要翻译：提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据，计算系统。该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。该方法还包括提供用于在从总线控制器接收到命令分组之后从属总线控制器接收到用于命令分组的第一信令间隔的从总线控制器向主总线控制器发送确认的装置。

6. 发明申请

US20070073919A1 Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes 失效
标题翻译：允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法
公开(公告)号：US20070073919A1
公开(公告)日：2007-03-29
申请号：US11226967
申请日：2005-09-15
申请人： George Daly , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： George Daly , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.
摘要翻译：数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控制器的第二处理。存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点与第二个地址关联的域指示符。

7. 发明申请

US20060190636A1 Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations 失效
标题翻译：在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置
公开(公告)号：US20060190636A1
公开(公告)日：2006-08-24
申请号：US11054183
申请日：2005-02-09
申请人： George Daly , James Fields
发明人： George Daly , James Fields
IPC分类号： G06F13/28
CPC分类号： G06F12/0835 , G06F13/28
摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.
摘要翻译：公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。最初，外围设备发出多高速缓存行DMA请求。多高速缓存行DMA请求被缓存内存窥探。然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。

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