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1. 发明申请

US20060179248A1 Data processing system and method for efficient storage of metadata in a system memory 失效
标题翻译：用于在系统存储器中有效存储元数据的数据处理系统和方法
公开(公告)号：US20060179248A1
公开(公告)日：2006-08-10
申请号：US11055640
申请日：2005-02-10
申请人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
发明人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

2. 发明申请

US20080028156A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT STORAGE OF METADATA IN A SYSTEM MEMORY 有权
标题翻译：数据处理系统和方法，用于在系统存储器中有效存储元数据
公开(公告)号：US20080028156A1
公开(公告)日：2008-01-31
申请号：US11836908
申请日：2007-08-10
申请人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
发明人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

3. 发明申请

US20060179183A1 Single burst completion of multiple writes at buffered DIMMs 审中-公开
标题翻译：在缓冲DIMM上单次完成多次写入
公开(公告)号：US20060179183A1
公开(公告)日：2006-08-10
申请号：US11054372
申请日：2005-02-09
申请人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
发明人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/161 , G11C5/04
摘要： Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.
摘要翻译：在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。因此，针对同一DIMM的多个写入被缓存。当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

4. 发明申请

US20060179206A1 Programmable bank/timer address folding in memory devices 失效
公开(公告)号：US20060179206A1
公开(公告)日：2006-08-10
申请号：US11054066
申请日：2005-02-09
申请人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
发明人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
IPC分类号： G06F12/06
CPC分类号： G06F13/1647 , G11C5/04 , Y02D10/14
摘要： A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

5. 发明申请

US20080091905A1 EXECUTING BACKGROUND WRITES TO IDLE DIMMS 失效
标题翻译：执行背景写入空白
公开(公告)号：US20080091905A1
公开(公告)日：2008-04-17
申请号：US11951735
申请日：2007-12-06
申请人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
发明人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1626
摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.
摘要翻译：内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

6. 发明申请

US20060179213A1 Executing background writes to idle DIMMs 失效
标题翻译：执行后台写入空闲DIMM
公开(公告)号：US20060179213A1
公开(公告)日：2006-08-10
申请号：US11054447
申请日：2005-02-09
申请人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
发明人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1626
摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.
摘要翻译：内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

7. 发明申请

US20060179237A1 Method and apparatus for performing data prefetch in a multiprocessor system 失效
标题翻译：在多处理器系统中执行数据预取的方法和装置
公开(公告)号：US20060179237A1
公开(公告)日：2006-08-10
申请号：US11054173
申请日：2005-02-09
申请人： James Fields , Benjiman Goodman , Guy Guthrie , Jeffrey Stuecheli
发明人： James Fields , Benjiman Goodman , Guy Guthrie , Jeffrey Stuecheli
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0831 , G06F12/0851
摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.
摘要翻译：公开了一种用于在多处理器系统中执行数据预取的方法和装置。多处理器系统包括多个处理器，每个具有高速缓冲存储器。缓存存储器被细分成多个片段。一组预取请求最初由多处理器系统中的请求处理器发出。每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

8. 发明申请

US20070266126A1 DATA PROCESSING SYSTEM AND METHOD OF DATA PROCESSING SUPPORTING TICKET-BASED OPERATION TRACKING 审中-公开
标题翻译：数据处理系统和数据处理方法支持基于票单的操作跟踪
公开(公告)号：US20070266126A1
公开(公告)日：2007-11-15
申请号：US11279643
申请日：2006-04-13
申请人： Leo Clark , James Fields , Benjiman Goodman , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Benjiman Goodman , William Starke , Jeffrey Stuecheli
IPC分类号： G06F15/173
CPC分类号： G06F12/0831 , G06F12/0897 , G06F12/1458
摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.
摘要翻译：数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送处理单位。该通信包括具有请求的操作和表示对请求的系统响应的组合响应。至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

9. 发明申请

US20060179272A1 Data processing system, method and interconnect fabric for partial response accumulation in a data processing system 失效
标题翻译：数据处理系统，数据处理系统部分响应累积的方法和互连结构
公开(公告)号：US20060179272A1
公开(公告)日：2006-08-10
申请号：US11055297
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F15/00
CPC分类号： G06F13/385 , G06F9/546
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个处理单位。互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应响应。

10. 发明申请

US20060179254A1 Data processing system, method and interconnect fabric supporting destination data tagging 有权
标题翻译：数据处理系统，方法和互连结构支持目标数据标记
公开(公告)号：US20060179254A1
公开(公告)日：2006-08-10
申请号：US11055405
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译：数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

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