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21. 发明申请

US20080259687A1 Integrated Circuits and Methods of Manufacturing Thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20080259687A1
公开(公告)日：2008-10-23
申请号：US11737617
申请日：2007-04-19
申请人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
发明人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
IPC分类号： G11C5/00 , H01R43/00
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译：本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

22. 发明申请

US20080251833A1 Integrated circuits and methods of manufacture 审中-公开
标题翻译：集成电路和制造方法
公开(公告)号：US20080251833A1
公开(公告)日：2008-10-16
申请号：US11786751
申请日：2007-04-12
申请人： Michael Specht , Franz Hofmann , Nicolas Nagel
发明人： Michael Specht , Franz Hofmann , Nicolas Nagel
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L25/105 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the invention, integrated circuits and methods of manufacturing integrated circuits are provided. In an embodiment of the invention, an integrated circuit having at least one memory cell is provided. The memory cell includes a dielectric layer disposed above a charge storage region, a word line disposed above the dielectric layer, and a control line disposed at least partially above at least one sidewall of the dielectric layer.
摘要翻译：在本发明的各种实施例中，提供集成电路和制造集成电路的方法。在本发明的实施例中，提供了具有至少一个存储单元的集成电路。存储单元包括设置在电荷存储区域上方的电介质层，设置在电介质层上方的字线以及至少部分地设置在电介质层的至少一个侧壁上方的控制线。

23. 发明授权

US07344923B2 NROM semiconductor memory device and fabrication method 失效
标题翻译： NROM半导体存储器件及其制造方法
公开(公告)号：US07344923B2
公开(公告)日：2008-03-18
申请号：US11282904
申请日：2005-11-18
申请人： Franz Hofmann , Erhard Landgraf , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Michael Specht
IPC分类号： H01L21/82
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/7923
摘要： An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. The dielectric suitable for charge trapping along rows in a first direction and alone columns in a second direction in trenches of a semiconductor substrate. Source/drain regions are provided between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns. Isolation trenches are provided in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate. The isolation trenches are filled with an insulation material. Word lines are provided for connecting respective rows of u-shaped MOSFETs.
摘要翻译：公开了一种NROM半导体存储器件及其制造方法。根据一个方面，一种用于制造NROM半导体存储器件的方法可以包括提供多个彼此间隔开并具有多层电介质的u形MOSFET。适合于在半导体衬底的沟槽中沿着第一方向沿着行电荷捕获并在第二方向上单独的列的电介质。源极/漏极区域设置在平行于列的行之间的间隔中的u形MOSFET之间。在相邻列的u形MOSFET之间的源极/漏极区域中提供了直到半导体衬底中的特定深度的隔离沟槽。隔离槽填充绝缘材料。字线用于连接各行的u形MOSFET。

24. 发明申请

US20070096198A1 Non-volatile memory cells and method for fabricating non-volatile memory cells 审中-公开
标题翻译：非易失性存储单元和用于制造非易失性存储单元的方法
公开(公告)号：US20070096198A1
公开(公告)日：2007-05-03
申请号：US11262309
申请日：2005-10-28
申请人： Franz Hofmann , Johannes Luyken , Michael Specht , Wolfgang Rosner
发明人： Franz Hofmann , Johannes Luyken , Michael Specht , Wolfgang Rosner
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L29/40117 , H01L29/42352 , H01L29/785
摘要： The invention relates to non-volatile memory cells. Further, the invention relates to a method for fabricating non-volatile memory cells. Memory cells are formed on a semiconductor wafer having a protruding element with a top surface. A transistor is formed having a first part, a second part, and a third part. The first part includes a first junction region and a first charge trapping layer on the top surface. The second part includes a second junction region and charge trapping layer on the top surface. The third part has a gate electrode and a gate dielectric layer at least partially on sidewalls of the protruding element. The gate electrode contacts the first and second charge trapping layers.
摘要翻译：本发明涉及非易失性存储单元。此外，本发明涉及一种制造非易失性存储单元的方法。存储单元形成在具有顶表面的突出元件的半导体晶片上。晶体管形成有第一部分，第二部分和第三部分。第一部分包括顶表面上的第一接合区域和第一电荷俘获层。第二部分包括顶表面上的第二结区和电荷捕获层。第三部分至少部分地在突出元件的侧壁上具有栅极电极和栅极电介质层。栅电极接触第一和第二电荷捕获层。

25. 发明申请

US20070023808A1 Semiconductor memory, the fabrication thereof and a method for operating the semiconductor memory 失效
标题翻译：半导体存储器，其制造和半导体存储器的操作方法
公开(公告)号：US20070023808A1
公开(公告)日：2007-02-01
申请号：US11193026
申请日：2005-07-29
申请人： Michael Specht , Wolfgang Roesner , Franz Hofmann
发明人： Michael Specht , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/7887 , G11C16/0475 , H01L29/513 , H01L29/66833 , H01L29/7923
摘要： A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate (1), a second doping region (7) disposed in the substrate (1), a channel region (22) disposed in the substrate (1) between the first doping region (6) and the second doping region (7), a charge-trapping layer stack (2) disposed on the substrate (1), on the channel region (22), on a portion of the first doping region (6) and on a portion of the second doping region (7). Each memory cell (21-1) further comprises a conductive layer (3) disposed on the charge-trapping layer stack (2), wherein the conductive layer (3) is electrically floating. A dielectric layer (4) is disposed on a top surface of the conductive layer (3) and on sidewalls (23) of the conductive layer (3). The first line (15-1) extends along a first direction and is coupled to the first doping region (6), and the second line (15-2; 16-1) extends along the first direction and is coupled to the second doping region (7). The at least one wordline (5-1) extends along a second direction and is disposed on the dielectric layer (4).
摘要翻译：一种具有多个存储单元（21-1）的半导体存储器，所述半导体存储器具有衬底（1），至少一个字线（5-1），第一（15-1）和第二线（15-2） ; 16-1），其中多个存储单元（21-1）中的每一个包括设置在所述衬底（1）中的第一掺杂区域（6），设置在所述衬底（1）中的第二掺杂区域（7）设置在第一掺杂区域（6）和第二掺杂区域（7）之间的衬底（1）中的沟道区域（22），设置在衬底（1）上的电荷捕获层堆叠（2）在第一掺杂区域（6）的一部分上和第二掺杂区域（7）的一部分上的区域（22）。每个存储单元（21-1）还包括设置在电荷捕获层堆叠（2）上的导电层（3），其中导电层（3）是电浮置的。介电层（4）设置在导电层（3）的顶表面和导电层（3）的侧壁（23）上。第一线（15-1）沿着第一方向延伸并且耦合到第一掺杂区域（6），并且第二线路（15-2; 16-1）沿着第一方向延伸并且耦合到第二掺杂地区（7）。所述至少一个字线（5-1）沿着第二方向延伸并且设置在所述电介质层（4）上。

26. 发明申请

US20070018201A1 Non-volatile memory cells and methods for fabricating non-volatile memory cells 有权
标题翻译：非易失性存储单元和用于制造非易失性存储单元的方法
公开(公告)号：US20070018201A1
公开(公告)日：2007-01-25
申请号：US11187693
申请日：2005-07-22
申请人： Michael Specht , Franz Hofmann , Johannes Luyken
发明人： Michael Specht , Franz Hofmann , Johannes Luyken
IPC分类号： H01L27/10
CPC分类号： H01L27/11568 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/785
摘要： The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.
摘要翻译：本发明涉及一种用于制造堆叠的非易失性存储单元的方法。此外，本发明涉及堆叠的非易失性存储单元。本发明特别涉及具有非易失性堆叠存储单元的非易失性NAND存储器的领域。层叠的非易失性存储单元形成在具有体半导体基板和SOI半导电层的半导体晶片上，并且被布置为体FinFET晶体管，并且SOI FinFet晶体管布置在体FinFET晶体管的顶部。 FinFET晶体管和SOI FinFet晶体管都连接到公共的电荷俘获层。具有侧壁的字线被布置在所述图案化的电荷捕获层的顶部上，并且间隔氧化物层被布置在所述字线的侧壁上。

27. 发明申请

US20060261403A1 Semiconductor memory device and method of production 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20060261403A1
公开(公告)日：2006-11-23
申请号：US11135002
申请日：2005-05-23
申请人： Franz Hofmann , Johannes Luyken , Michael Specht
发明人： Franz Hofmann , Johannes Luyken , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4232 , H01L29/42352 , H01L29/66833
摘要： An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence along the direction of the wordlines, connected alternatingly to one of two adjacent wordlines.
摘要翻译：电荷俘获存储器单元阵列和横向于字线的并行字线和并行位线的多个排列在衬底表面上。栅电极位于字线和位线之间，并且沿着字线方向的顺序交替地连接到两个相邻字线之一。

28. 发明申请

US20060181925A1 Nonvolatile memory cell arrangement 有权
标题翻译：非易失性存储单元布置
公开(公告)号：US20060181925A1
公开(公告)日：2006-08-17
申请号：US11283572
申请日：2005-11-18
申请人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
发明人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.
摘要翻译：存储晶体管被布置成多个行和列。第一列的每个存储晶体管的第一源极/漏极端子连接到第一金属化平面中的导电导体轨道，并且与第一列相邻的第二列的每个存储晶体管的第一源极/漏极端子被连接到第二金属化平面中的导电导体轨道。

29. 发明申请

US20060175666A1 Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权
公开(公告)号：US20060175666A1
公开(公告)日：2006-08-10
申请号：US11324803
申请日：2006-01-03
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

30. 发明申请

US20050269617A1 Semi-conductor component with condensators buried in the substrate and insulated component layer thereof 有权
标题翻译：半导体部件与冷凝器埋在基板和绝缘部件层中
公开(公告)号：US20050269617A1
公开(公告)日：2005-12-08
申请号：US10523944
申请日：2003-09-13
申请人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rosner , Michael Specht
发明人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rosner , Michael Specht
IPC分类号： H01L21/02 , H01L21/334 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/10867 , H01L27/1203 , H01L28/82 , H01L29/66181 , H01L29/945
摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.
摘要翻译：提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

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