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21. 发明申请

US20080023704A1 Display Device and Fabrication Method Thereof 审中-公开
标题翻译：显示装置及其制作方法
公开(公告)号：US20080023704A1
公开(公告)日：2008-01-31
申请号：US11782701
申请日：2007-07-25
申请人： TAKESHI NODA , Takahiro Kamo , Eiji Oue , Mutsuko Hatano , Takeshi Sato
发明人： TAKESHI NODA , Takahiro Kamo , Eiji Oue , Mutsuko Hatano , Takeshi Sato
IPC分类号： H01L29/04 , H01L21/00
CPC分类号： H01L29/04 , H01L21/02532 , H01L21/02683 , H01L21/02691 , H01L27/1248 , H01L27/1285
摘要： The present invention obtains a system-in-panel display device using a high-performance thin film transistor by suppressing aggregation of a molten semiconductor at the time of allowing strip-like pseudo-single crystal to grow continuously with a direction control by radiating beams of continuous oscillation laser to a semiconductor film made of silicon while scanning. A display device includes a silicon nitride film formed on the insulation substrate, a silicon oxide film formed on the silicon nitride film, a semiconductor film formed on the silicon oxide film, and a thin film transistor which uses the semiconductor film. Here, the silicon oxide film is constituted of a first silicon oxide film formed using SiH4 and N2O as raw material gases and a second silicon oxide film formed using a TEOS gas as a raw material gas, and the semiconductor film is made of pseudo-single crystal having strip-like grains.
摘要翻译：本发明通过抑制带状伪单晶在通过辐射光束的方向控制而连续生长时，通过抑制熔融半导体的聚集来获得使用高性能薄膜晶体管的面板内系统显示装置在扫描时对由硅制成的半导体膜进行连续振荡激光。显示装置包括形成在绝缘基板上的氮化硅膜，形成在氮化硅膜上的氧化硅膜，形成在氧化硅膜上的半导体膜，以及使用该半导体膜的薄膜晶体管。这里，氧化硅膜由使用SiH 4 N 2和N 2 O作为原料气体形成的第一氧化硅膜和使用TEOS形成的第二氧化硅膜构成气体作为原料气体，半导体膜由具有带状粒子的假单晶构成。

22. 发明申请

US20070072349A1 Manufacturing method of a display device 有权
标题翻译：显示装置的制造方法
公开(公告)号：US20070072349A1
公开(公告)日：2007-03-29
申请号：US11509739
申请日：2006-08-25
申请人： Takuo Kaitoh , Eiji Oue , Toshihiko Itoga
发明人： Takuo Kaitoh , Eiji Oue , Toshihiko Itoga
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/02675 , H01L21/2026 , H01L27/1285 , H01L27/1296 , H01L29/04
摘要： The present invention provides a manufacturing method of a display device which can decrease the lowering of a yield rate of the display device attributed to the aggregations generated by pseudo single crystallization of a silicon film. A manufacturing method of a display device includes a semiconductor film reforming step which reforms a semiconductor film into a second state in which the semiconductor film possesses elongated crystalline particles by radiating a laser beam to the semiconductor film in a first state, an aggregation detecting step which detects the aggregation of the semiconductor film which is generated in the semiconductor film reforming step, and a defect determination step which determines a product as a defective product when a position of the aggregation is present in the inside of the predetermined region and determines the product as a good product when the position of the aggregation is present outside the predetermined region.
摘要翻译：本发明提供一种显示装置的制造方法，其能够降低归因于硅膜的伪单晶化产生的聚集的显示装置的成品率的降低。显示装置的制造方法包括：半导体膜重整工序，其将第一状态下的半导体膜照射激光，将半导体膜改性为半导体膜具有细长结晶粒子的第二状态，聚集检测步骤，检测在半导体膜重整步骤中产生的半导体膜的聚集，以及缺陷确定步骤，当聚集的位置存在于预定区域的内部时，将产品确定为不合格品，并将产品确定为当聚集的位置存在于预定区域之外时，产品是良好的。

23. 发明授权

US06974977B2 Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US06974977B2
公开(公告)日：2005-12-13
申请号：US10457428
申请日：2003-06-10
申请人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
发明人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
IPC分类号： H01L29/72 , G02B6/42 , H01L21/331 , H01L29/737 , H03F3/45
CPC分类号： H01L29/66242 , G02B6/4251 , G02B6/4274 , H01L29/7375 , H01L29/7378 , H03F3/45085 , H03F3/45089 , H03F2200/372 , H03F2203/45311 , H03F2203/45574 , H03F2203/45612 , H03F2203/45652 , H03F2203/45722
摘要： A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
摘要翻译：提供了具有高可靠性和高增益的双极晶体管，并且特别适用于高速运行。双极晶体管以高精度工作，即使在集电极电压变化时也不会对集电极电流产生实质性的变化。与传统的集电极电流双极晶体管相比，它具有较小的变化，同时确保了高速性能和高增益。在一个示例中，基极区域中的带隙小于发射极和集电极区域中的带隙。带隙在与发射极区域的结点附近是恒定的，并且朝着与集电极区域的结点减小。单晶硅/锗通常用于基极区域。

24. 发明授权

US06600178B1 Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US06600178B1
公开(公告)日：2003-07-29
申请号：US09599741
申请日：2000-06-23
申请人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
发明人： Katsuyoshi Washio , Reiko Hayami , Hiromi Shimamoto , Masao Kondo , Katsuya Oda , Eiji Oue , Masamichi Tanabe
IPC分类号： H01L29737
CPC分类号： H01L29/66242 , G02B6/4251 , G02B6/4274 , H01L29/7375 , H01L29/7378 , H03F3/45085 , H03F3/45089 , H03F2200/372 , H03F2203/45311 , H03F2203/45574 , H03F2203/45612 , H03F2203/45652 , H03F2203/45722
摘要： A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.
摘要翻译：提供了具有高可靠性和高增益的双极晶体管，并且特别适用于高速运行。双极晶体管以高精度工作，即使在集电极电压变化时也不会对集电极电流产生实质性的变化。与传统的集电极电流双极晶体管相比，它具有较小的变化，同时确保了高速性能和高增益。在一个示例中，基极区域中的带隙小于发射极和集电极区域中的带隙。带隙在与发射极区域的结点附近是恒定的，并且朝着与集电极区域的结点减小。单晶硅/锗通常用于基极区域。

25. 发明授权

US06476450B2 BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
标题翻译： BICMOS半导体集成电路器件及其制造工艺
公开(公告)号：US06476450B2
公开(公告)日：2002-11-05
申请号：US09808952
申请日：2001-03-16
申请人： Masao Kondo , Katsuyoshi Washio , Eiji Oue , Hiromi Shimamoto
发明人： Masao Kondo , Katsuyoshi Washio , Eiji Oue , Hiromi Shimamoto
IPC分类号： H01L29732
CPC分类号： H01L27/0623 , H01L21/8249 , H01L2924/0002 , H01L2924/00
摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.
摘要翻译：本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。

26. 发明授权

US07535024B2 Display device and fabrication method thereof 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US07535024B2
公开(公告)日：2009-05-19
申请号：US11600164
申请日：2006-11-16
申请人： Eiji Oue , Toshihiko Itoga , Toshiki Kaneko , Daisuke Sonoda , Takeshi Kuriyagawa
发明人： Eiji Oue , Toshihiko Itoga , Toshiki Kaneko , Daisuke Sonoda , Takeshi Kuriyagawa
IPC分类号： H01L29/04
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/78696 , H01L2029/7863
摘要： The present invention provides a fabrication method of a display device which aims at the reduction of fabricating man-hours. In a fabrication method of a display device having a thin film transistor in which a gate electrode includes a first gate electrode and a second gate electrode which is overlapped to the first gate electrode and has a size thereof in the channel direction set smaller than the corresponding size of the first gate electrode, the semiconductor layer includes a channel region which is overlapped to the second gate electrode, a first impurity region which is overlapped to the first gate electrode and is formed outside the second gate electrode, a second impurity region which is formed outside the gate electrode, and a third conductive impurity region which is formed outside the gate electrode and the second impurity region, the first impurity region, the second impurity region and the third impurity region are respectively formed of the same conductive type, the impurity concentration of the first impurity region is lower than the impurity concentration of the third impurity region, and the impurity concentration of the second impurity region is lower than the impurity concentration of the first impurity region, impurities are collectively implanted into both of the first and second impurity regions such that the impurities are implanted into the first impurity region by way of the first gate electrode and the impurities are implanted into the second impurity region such that a peak position of the impurity concentration in the depth direction is positioned below the semiconductor layer thus lowering the impurity concentration of the second impurity region than the impurity concentration of the first impurity region.
摘要翻译：本发明提供了一种旨在减少制造工时的显示装置的制造方法。在具有薄膜晶体管的显示装置的制造方法中，其中栅电极包括第一栅极和与第一栅电极重叠并且具有小于相应的沟道方向的尺寸的第二栅电极第一栅电极的尺寸，半导体层包括与第二栅电极重叠的沟道区，与第一栅电极重叠并形成在第二栅电极外的第一杂质区，第二杂质区，形成在栅极电极外部的第三导电杂质区域和形成在栅电极和第二杂质区域外的第三导电杂质区域，第一杂质区域，第二杂质区域和第三杂质区域分别由相同的导电类型形成，杂质第一杂质区域的浓度低于第三杂质区域的杂质浓度第二杂质区域的杂质浓度低于第一杂质区域的杂质浓度，将杂质共同地注入到第一和第二杂质区域中，使得杂质通过第一栅电极注入第一杂质区域并且将杂质注入到第二杂质区域中，使得深度方向上的杂质浓度的峰值位置位于半导体层的下方，从而降低第二杂质区域的杂质浓度比第一杂质区域的杂质浓度降低。

27. 发明申请

US20080142803A1 Display device and manufacturing method thereof 审中-公开
标题翻译：显示装置及其制造方法
公开(公告)号：US20080142803A1
公开(公告)日：2008-06-19
申请号：US12000403
申请日：2007-12-12
申请人： Takuo Kaitoh , Eiji Oue
发明人： Takuo Kaitoh , Eiji Oue
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L27/1222 , H01L27/1296 , H01L29/04 , H01L29/458 , H01L29/78696
摘要： With the present invention, it is possible to provide a high quality image display by suppressing such faults as malfunction of a circuit or leakage of a current due to hump caused by the characteristic of a thin film transistor at a channel edge portion.An edge portion 302 of a polysilicon layer 301 functioning as a channel layer is converted into a noncrystalline or fine crystalline area. Because a silicon semiconductor film at the channel edge portion 302 is in the fine crystalline or noncrystalline state, a current flowing there is extremely small, or a current does not flow there. Thus, even when a threshold voltage Vth at a channel central portion is different from that at a channel edge portion, performance of the entire thin film transistor film is little affected, so that display faults due to hump are prevented.
摘要翻译：通过本发明，可以通过抑制电路的故障或由沟道边缘部分的薄膜晶体管的特性引起的由于隆起引起的电流的泄漏而提供高质量的图像显示。用作沟道层的多晶硅层301的边缘部分302被转换成非结晶或细晶体区域。由于沟道边缘部302处的硅半导体膜处于微细或非结晶状态，所以流过的电流极小，或者电流不流过。因此，即使在通道中心部分的阈值电压Vth与通道边缘部分的阈值电压Vth不同时，薄膜晶体管膜整体的性能也受到很小的影响，从而防止由于突起引起的显示故障。

28. 发明申请

US20070108449A1 Display device and fabrication method thereof 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20070108449A1
公开(公告)日：2007-05-17
申请号：US11600164
申请日：2006-11-16
申请人： Eiji Oue , Toshihiko Itoga , Toshiki Kaneko , Daisuke Sonoda , Takeshi Kuriyagawa
发明人： Eiji Oue , Toshihiko Itoga , Toshiki Kaneko , Daisuke Sonoda , Takeshi Kuriyagawa
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/78696 , H01L2029/7863
摘要： The present invention provides a fabrication method of a display device which aims at the reduction of fabricating man-hours. In a fabrication method of a display device having a thin film transistor in which a gate electrode includes a first gate electrode and a second gate electrode which is overlapped to the first gate electrode and has a size thereof in the channel direction set smaller than the corresponding size of the first gate electrode, the semiconductor layer includes a channel region which is overlapped to the second gate electrode, a first impurity region which is overlapped to the first gate electrode and is formed outside the second gate electrode, a second impurity region which is formed outside the gate electrode, and a third conductive impurity region which is formed outside the gate electrode and the second impurity region, the first impurity region, the second impurity region and the third impurity region are respectively formed of the same conductive type, the impurity concentration of the first impurity region is lower than the impurity concentration of the third impurity region, and the impurity concentration of the second impurity region is lower than the impurity concentration of the first impurity region, impurities are collectively implanted into both of the first and second impurity regions such that the impurities are implanted into the first impurity region by way of the first gate electrode and the impurities are implanted into the second impurity region such that a peak position of the impurity concentration in the depth direction is positioned below the semiconductor layer thus lowering the impurity concentration of the second impurity region than the impurity concentration of the first impurity region.
摘要翻译：本发明提供了一种旨在减少制造工时的显示装置的制造方法。在具有薄膜晶体管的显示装置的制造方法中，其中栅电极包括第一栅极和与第一栅电极重叠并且具有小于相应的沟道方向的尺寸的第二栅电极第一栅电极的尺寸，半导体层包括与第二栅电极重叠的沟道区，与第一栅电极重叠并形成在第二栅电极外的第一杂质区，第二杂质区，形成在栅电极外部的第三导电杂质区域和形成在栅电极和第二杂质区域外的第三导电杂质区域，第一杂质区域，第二杂质区域和第三杂质区域分别由相同的导电型形成，杂质第一杂质区域的浓度低于第三杂质区域的杂质浓度第二杂质区域的杂质浓度低于第一杂质区域的杂质浓度，将杂质共同地注入到第一和第二杂质区域中，使得杂质通过第一栅电极注入第一杂质区域并且将杂质注入到第二杂质区域中，使得深度方向上的杂质浓度的峰值位置位于半导体层的下方，从而降低第二杂质区域的杂质浓度比第一杂质区域的杂质浓度降低。

29. 发明授权

US06905934B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06905934B2
公开(公告)日：2005-06-14
申请号：US10086689
申请日：2002-03-04
申请人： Takashi Hashimoto , Kouji Mikami , Tsutomu Udo , Masao Kondo , Eiji Oue
发明人： Takashi Hashimoto , Kouji Mikami , Tsutomu Udo , Masao Kondo , Eiji Oue
IPC分类号： H01L21/28 , H01L21/331 , H01L21/337 , H01L21/768 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L29/737 , H01L29/80
CPC分类号： H01L29/66916 , H01L21/8249 , H01L29/802
摘要： The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown selectively in an aperture formed by removing a silicon nitride film so as to form under cut.
摘要翻译：本发明提供了具有改进性能的双极晶体管。通过在发射器孔径的侧表面上进行氧化处理形成包含氧化硅膜的绝缘膜，然后选择性地在由除去氮化硅膜形成的孔中生长由SiGe组成的外延层，以形成下面切。

30. 发明申请

US20050001238A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050001238A1
公开(公告)日：2005-01-06
申请号：US10855378
申请日：2004-05-28
申请人： Eiji Oue , Katsuyoshi Washio , Hiromi Shimamoto , Katsuya Oda , Makoto Miura
发明人： Eiji Oue , Katsuyoshi Washio , Hiromi Shimamoto , Katsuya Oda , Makoto Miura
IPC分类号： H01L21/331 , H01L29/732 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/66287 , H01L29/7322
摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.
摘要翻译：提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。外部基极和集电极区域通过绝缘体彼此分离。

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