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21. 发明授权

US08384165B2 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
标题翻译：门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中
公开(公告)号：US08384165B2
公开(公告)日：2013-02-26
申请号：US12140773
申请日：2008-06-17
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L29/49 , H01L29/51
CPC分类号： H01L29/49 , G02B6/3897 , G02B6/445 , H01L29/51 , H02G15/117
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

22. 发明授权

US07956401B2 Bi-axial texturing of high-K dielectric films to reduce leakage currents 有权
标题翻译：高K电介质膜的双轴纹理化以减少漏电流
公开(公告)号：US07956401B2
公开(公告)日：2011-06-07
申请号：US12574479
申请日：2009-10-06
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L21/336
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.
摘要翻译：本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。所公开的方法包括提供衬底，然后沉积辅助有离子束的高K电介质材料，以便优先形成具有选定结晶取向的晶格。所得介电膜在晶界处具有高度的结晶取向。另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。结果是在膜的晶界处具有高度结晶取向的电介质膜。

23. 发明申请

US20080268650A1 TRIPLE POLY-SI REPLACEMENT SCHEME FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的三重多重替换方案
公开(公告)号：US20080268650A1
公开(公告)日：2008-10-30
申请号：US11742003
申请日：2007-04-30
申请人： Chungho Lee , Huaqiang Wu , Wai Lo , Hiroyuki Kinoshita
发明人： Chungho Lee , Huaqiang Wu , Wai Lo , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11573 , H01L21/28282
摘要： A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.
摘要翻译：提供了替换存储器件的存储元件周围的顶部氧化物的方法。该方法可以包括在核心区域中去除核心的第一多核和第一顶部氧化物，而不去除半导体衬底上的外围区域中的周边第一多晶硅; 在所述芯区域中的存储元件周围和所述周边区域的所述外围第一聚四氟乙烯上形成第二顶部氧化物; 在所述芯和外围区域中在所述半导体衬底上形成第二聚合物; 去除所述周边区域中的所述第二聚合物和第二顶部氧化物; 以及在所述芯和外围区域中在所述半导体衬底上形成第三聚合物。

24. 发明授权

US07365015B2 Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material 有权
标题翻译：使用Si1-xGex作为牺牲材料的具有受控栅极轮廓和长度的镶嵌金属栅极工艺
公开(公告)号：US07365015B2
公开(公告)日：2008-04-29
申请号：US10889901
申请日：2004-07-13
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，PolyS 1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

25. 发明授权

US07341978B2 Superconductor wires for back end interconnects 有权
标题翻译：用于后端互连的超导线
公开(公告)号：US07341978B2
公开(公告)日：2008-03-11
申请号：US11072158
申请日：2005-03-04
申请人： Shiqun Gu , Wai Lo , Hong Lin
发明人： Shiqun Gu , Wai Lo , Hong Lin
IPC分类号： H01L33/00
CPC分类号： H01L21/76838 , H01L21/76834 , H01L23/53285 , H01L2924/0002 , H01L2924/00
摘要： An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide. The superconducting material is in some embodiments at least one of an organic compound such as a potassium doped buckminsterfullerene, a cesium doped buckminsterfullerene, and other carbon containing compounds, a metallic material such as an inter-metallic material like Nb—Ti alloys and other substances formed by alloying metals, and an inorganic compound such as YBa2Cu3O7-x, (Pb,Bi)2Sr2Ca2Cu3O10-x and its derivatives, HgBaCaCuO and its derivatives, and TI—Ba—Ca—Cu—O and its derivatives.
摘要翻译：对由超导材料形成的导电互连的集成电路的改进。以这种方式，可以使导电互连非常小，但仍然具有足够的导电性。在各种实施例中，所有导电互连由超导材料形成。在一些实施例中，导电互连由各种不同的超导材料形成。在一个实施例中，只有后端导电互连由超导材料形成。在一些实施例中，没有由超导材料形成通孔。互导体电介质层优选由氧化硅形成，并且有时所有的互导电介质层均由氧化硅形成。在一些实施方案中，超导材料是有机化合物，例如掺杂钾的巴克敏斯特富勒烯，掺杂铯的德克敏斯特富勒烯和其它含碳化合物中的至少一种，金属材料如诸如Nb-Ti合金的金属间材料和其它物质由金属合金化而形成的无机化合物，例如YBa 2 N 3 O 7-x X，（Pb，Bi）2 Sr 2 O 2和其衍生物HgBaCaCuO及其衍生物和TI-Ba-Ca-Cu-O及其衍生物。

26. 发明授权

US07312127B2 Incorporating dopants to enhance the dielectric properties of metal silicates 有权
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US07312127B2
公开(公告)日：2007-12-25
申请号：US11389643
申请日：2006-03-23
申请人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763 , B05D3/02
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含III族金属。

27. 发明申请

US20070099341A1 Method of making stacked die package 有权
标题翻译：制造堆叠模具包装的方法
公开(公告)号：US20070099341A1
公开(公告)日：2007-05-03
申请号：US11524457
申请日：2006-09-20
申请人： Wai Lo
发明人： Wai Lo
IPC分类号： H01L21/00
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3107 , H01L23/3128 , H01L23/4951 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/01004 , H01L2924/00011 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A method of making a stacked die package (39) includes placing a first flip chip die (16) on a base carrier (12) and electrically connecting the first flip chip die (16) to the base carrier (12). A second flip chip die (18) is attached back-to-back to the first flip chip die (16) and electrically connected to the base carrier (12) with a plurality of insulated wires (20). A mold compound (36) is formed over the first and second dice and one surface of the base carrier.
摘要翻译：制造堆叠管芯封装（39）的方法包括将第一倒装芯片裸片（16）放置在基座载体（12）上并将第一倒装芯片裸片（16）电连接到基座载体（12）。第二倒装芯片（18）背对背地安装到第一倒装芯片裸片（16），并用多个绝缘线（20）电连接到基座（12）。模制化合物（36）形成在第一和第二骰子和基底载体的一个表面上。

28. 发明授权

US07081406B2 Interconnect dielectric tuning 失效
标题翻译：互连电介质调谐
公开(公告)号：US07081406B2
公开(公告)日：2006-07-25
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
摘要翻译：对形成集成电路的方法的改进。形成蚀刻停止层以覆盖集成电路的前端处理层。形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

29. 发明申请

US20050127458A1 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US20050127458A1
公开(公告)日：2005-06-16
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/3115 , H01L21/316 , H01L29/76
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含IV族金属。

30. 发明授权

US08384146B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08384146B2
公开(公告)日：2013-02-26
申请号：US13428848
申请日：2012-03-23
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

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