专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060118919A1 Bi-axial texturing of high-K dielectric films to reduce leakage currents 失效
公开(公告)号：US20060118919A1
公开(公告)日：2006-06-08
申请号：US11007392
申请日：2004-12-07
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L29/04
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

2. 发明授权

US07956401B2 Bi-axial texturing of high-K dielectric films to reduce leakage currents 有权
标题翻译：高K电介质膜的双轴纹理化以减少漏电流
公开(公告)号：US07956401B2
公开(公告)日：2011-06-07
申请号：US12574479
申请日：2009-10-06
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L21/336
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.
摘要翻译：本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。所公开的方法包括提供衬底，然后沉积辅助有离子束的高K电介质材料，以便优先形成具有选定结晶取向的晶格。所得介电膜在晶界处具有高度的结晶取向。另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。结果是在膜的晶界处具有高度结晶取向的电介质膜。

3. 发明申请

US20050127458A1 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US20050127458A1
公开(公告)日：2005-06-16
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/3115 , H01L21/316 , H01L29/76
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含IV族金属。

4. 发明授权

US07619272B2 Bi-axial texturing of high-K dielectric films to reduce leakage currents 失效
标题翻译：高K电介质膜的双轴纹理化以减少漏电流
公开(公告)号：US07619272B2
公开(公告)日：2009-11-17
申请号：US11007392
申请日：2004-12-07
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L29/76
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.
摘要翻译：本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。所公开的方法包括提供衬底，然后沉积用于形成高K电介质膜的材料，并且还使用离子束来辅助优选形成具有选定结晶取向的晶格。所得的电介质膜在膜的晶界处具有高度的结晶取向度。另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。所得的电介质膜在膜的晶界处具有高度的结晶取向度。

5. 发明申请

US20060166496A1 Incorporating dopants to enhance the dielectric properties of metal silicates 有权
公开(公告)号：US20060166496A1
公开(公告)日：2006-07-27
申请号：US11389643
申请日：2006-03-23
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

6. 发明申请

US20050224358A1 Method for improved local planarity control during electropolishing 审中-公开
标题翻译：在电抛光过程中改进局部平面度控制的方法
公开(公告)号：US20050224358A1
公开(公告)日：2005-10-13
申请号：US10814059
申请日：2004-03-30
申请人： Byung-Sung Kwak , Jayanthi Pallinti , Sey-Shing Sun , William Barth , Wilbur Catabay
发明人： Byung-Sung Kwak , Jayanthi Pallinti , Sey-Shing Sun , William Barth , Wilbur Catabay
IPC分类号： C25D3/02 , C25D5/02 , C25D5/18 , C25D7/12 , C25D17/00 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/7684 , C25D3/02 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/32115 , H01L21/76877
摘要： A metal layer formed on a semiconductor wafer is planarized by applying sequentially a deplating step, a plating step, and a relaxation step in a removal cycle. A series of cycles are performed sequentially in one embodiment to comprise a pass. The removal cycle is repeated in sequence until the pass is completed. The respective deplating and plating rates are adjusted so that the ratios of deplating rates to plating rates progressively decrease from an initial pass to a final pass. Organic additives are added to the electrolytic plating solution to control the plating portion of the cycle in a topography dependant fashion.
摘要翻译：通过在去除循环中依次应用脱铝步骤，电镀步骤和弛豫步骤来平坦化在半导体晶片上形成的金属层。在一个实施例中，顺序执行一系列循环以包括通过。删除循环按顺序重复，直到通过完成。调整各自的脱镀和电镀速率，使得脱铝速率与电镀速率的比率从初始通过到最终通过逐渐降低。将有机添加剂添加到电解电镀溶液中以以地形依赖的方式控制循环的电镀部分。

7. 发明申请

US20060035455A1 Interconnect dielectric tuning 失效
公开(公告)号：US20060035455A1
公开(公告)日：2006-02-16
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

8. 发明申请

US20060118523A1 Planarization with reduced dishing 有权
标题翻译：平面化减少凹陷
公开(公告)号：US20060118523A1
公开(公告)日：2006-06-08
申请号：US11337460
申请日：2006-01-23
申请人： Wilbur Catabay , Wei-Jen Hsia , Hao Cui
发明人： Wilbur Catabay , Wei-Jen Hsia , Hao Cui
IPC分类号： B44C1/22 , C23F1/00 , C03C15/00
CPC分类号： B23H5/08 , C23F1/02 , C23F4/00 , C25F3/02 , H01L21/02063 , H01L21/32115 , H01L21/3212 , H01L21/32136 , H01L21/7684
摘要： A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.
摘要翻译：在衬底上形成平坦化层的方法，其中衬底被清洁，并且形成具有高部分和低部分的表面的层。电阻掩模形成在层的低部分上，但不在层的高部分之上。蚀刻层的表面，其中层的高部分暴露于蚀刻，但是电阻掩模下面的层的低部分不暴露于蚀刻。层的表面的蚀刻继续进行直到层的高部分与层的低部分基本相同的水平，从而提供层的表面的初始平坦化。电阻掩模从层的表面去除，并且层的所有表面被平坦化以提供平坦化层。

9. 发明申请

US20080308937A1 COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATION AND USE THEREOF 审中-公开
标题翻译：无铜半导体器件接口及其制造及其使用方法
公开(公告)号：US20080308937A1
公开(公告)日：2008-12-18
申请号：US12138595
申请日：2008-06-13
申请人： Wilbur Catabay , Julian Searle , Wei-Jen Hsia , Milan Prejda , Rohini Ranganathan , Lahcene Smati , Majid Milani
发明人： Wilbur Catabay , Julian Searle , Wei-Jen Hsia , Milan Prejda , Rohini Ranganathan , Lahcene Smati , Majid Milani
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L23/53223 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.
摘要翻译：本文提供了无铜半导体器件界面的实施例以及用于形成和/或利用其的方法。在一些实施例中，半导体结构可以包括具有暴露的含铜特征的衬底; 以及设置在衬底上方的无铜界面，并且在含铜特征和无铜界面的上表面之间提供导电互连，以便于将衬底电耦合到半导体器件，同时将半导体器件与含铜功能。

10. 发明申请

US20070178692A1 MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION 有权
标题翻译：形成用于铜层形成的障壁膜的多步法
公开(公告)号：US20070178692A1
公开(公告)日：2007-08-02
申请号：US11733673
申请日：2007-04-10
申请人： Wilbur Catabay , Zhihai Wang , Ping Li
发明人： Wilbur Catabay , Zhihai Wang , Ping Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76859 , H01L21/76864 , H01L21/76871 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization. Other embodiments include providing a substrate in a processing chamber and forming a copper seed layer on the substrate. The seed layer is implanted with barrier materials to form an implanted seed layer followed by bulk copper-containing layer formation. The substrate is annealed to form a final barrier layer. In a related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a copper seed layer on the first barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer. In yet another related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a second barrier layer on the first layer. A copper seed layer is formed on the second barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer.
摘要翻译：本发明的实施例包括一种形成具有双层铜阻挡层的铜互连的方法。该方法包括以下步骤：在处理室中提供衬底，所述衬底具有低K电介质绝缘层和绝缘层中的开口。在绝缘层和开口中形成钽/氮化钽的第一阻挡层。在第一阻挡层上形成第二阻挡层。第二阻挡层由选自钯，铬，钽，镁和钼的材料组成。在第二阻挡层上形成铜籽晶层，在籽晶层上形成体铜层。将衬底退火并进行可包括平坦化的进一步加工。其他实施例包括在处理室中提供衬底并在衬底上形成铜籽晶层。种子层被植入阻挡材料以形成植入的种子层，然后形成大块含铜层。将衬底退火以形成最终的阻挡层。在相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一阻挡层上形成铜籽晶层的步骤。在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。在另一相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一层上形成第二阻挡层的步骤。在第二阻挡层上形成铜籽晶层。在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式