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1. 发明申请

US20180212134A1 METHODOLOGY FOR FORMING A RESISTIVE ELEMENT IN A SUPERCONDUCTING STRUCTURE 审中-公开
公开(公告)号：US20180212134A1
公开(公告)日：2018-07-26
申请号：US15411090
申请日：2017-01-20
申请人： CORY EDWARD SHERMAN , SHAWN A. KEEBAUGH , REUBEN C. FERGUSON
发明人： CORY EDWARD SHERMAN , SHAWN A. KEEBAUGH , REUBEN C. FERGUSON
IPC分类号： H01L39/00 , H01L39/24
CPC分类号： G06F21/72 , H01L23/5228 , H01L23/53285 , H01L27/18
摘要： A method of forming a superconducting structure is provided that includes forming a superconducting element in a first dielectric layer, forming a protective pad formed from a resistive material over at least a portion of the superconducting element, forming a second dielectric layer overlying the first dielectric layer, and etching an opening through the second dielectric layer to the protective pad, such that no portion of the superconducting element is exposed in the opening. A cleaning process is performed on the superconducting structure, and a contact material fill with a resistive material is performed to fill the opening and form a resistive element in contact with the superconducting element through the protective pad.

2. 发明申请

US20180053689A1 PRECLEAN METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECT FABRICATION 审中-公开
公开(公告)号：US20180053689A1
公开(公告)日：2018-02-22
申请号：US15238394
申请日：2016-08-16
申请人： CHRISTOPHER F. KIRBY , SANDRO J. DI GIACOMO , MICHAEL RENNIE
发明人： CHRISTOPHER F. KIRBY , SANDRO J. DI GIACOMO , MICHAEL RENNIE
IPC分类号： H01L21/768 , H01L23/532 , H01L39/24
CPC分类号： H01L21/76891 , H01L21/02074 , H01L21/76883 , H01L23/53285
摘要： A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a superconducting interconnect element in a first dielectric layer, such that the superconducting interconnect element has a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The method also includes performing a plasma clean on a top surface of the first interconnect layer, and depositing a second dielectric layer over the first dielectric layer.

3. 发明申请

US20180005954A1 THROUGH-SILICON VIA WITH INSULATOR FILL 审中-公开
公开(公告)号：US20180005954A1
公开(公告)日：2018-01-04
申请号：US15198479
申请日：2016-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： DAVID W. ABRAHAM , JOHN M. COTTE , ISAAC LAUER
IPC分类号： H01L23/532 , H01L21/768 , H01L21/285 , H01L23/528 , H01L23/48
CPC分类号： H01L23/53285 , H01L21/76898 , H01L23/481
摘要： Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

4. 发明授权

US09577177B1 System and method for fabricating super conducting circuitry on both sides of an ultra-thin layer 有权
标题翻译：在超薄层的两侧制造超导电路的系统和方法
公开(公告)号：US09577177B1
公开(公告)日：2017-02-21
申请号：US15164365
申请日：2016-05-25
申请人： The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
发明人： Ari D. Brown , Vilem Mikula
IPC分类号： H01L39/24
CPC分类号： H01L23/53285 , H01L21/32058 , H01L21/743 , H01L21/76891
摘要： A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.
摘要翻译：一种在晶片中制造电路的方法包括在具有处理晶片的硅绝缘体晶片上沉积超导金属，用牺牲层涂覆晶片，并将晶片与第一环氧树脂结合到热氧化硅晶片。该方法包括翻转晶片，通过去除处理晶片，蚀刻掩埋氧化物层，沉积超导层，将晶片与使用环氧树脂的处理晶片接合的热氧化硅晶片，再次翻转晶片，从而使翻转的晶片变薄，使翻转的晶片变薄，从晶片上蚀刻掩埋氧化物层并从晶片上蚀刻牺牲层。结果是在超薄硅层的两侧具有超导电路的晶片。

5. 发明授权

US09297067B2 Fluorine passivation of dielectric for superconducting electronics 有权
标题翻译：超导电子学的电介质氟化钝化
公开(公告)号：US09297067B2
公开(公告)日：2016-03-29
申请号：US14137320
申请日：2013-12-20
申请人： Intermolecular, Inc.
发明人： Dipankar Pramanik , Andrew Steinbach
IPC分类号： C23C14/14 , C23C14/58 , H01L23/532 , H01L21/768 , H01L27/18
CPC分类号： C23C14/5806 , C23C14/14 , C23C14/16 , C23C14/5846 , H01L21/02123 , H01L21/02266 , H01L21/02321 , H01L21/02337 , H01L21/0234 , H01L21/3115 , H01L21/76826 , H01L21/76891 , H01L23/53285 , H01L23/5329 , H01L27/18 , H01L2924/0002 , Y10T428/265 , H01L2924/00
摘要： An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (
摘要翻译：制造用于超导电子器件的非晶硅（a-Si）电介质，通过在整个整个层中的氟钝化降低损耗角正切。通过在低温（<350℃，例如〜200℃）下的物理气相沉积形成a-Si的完整层或更薄的子层，以防止与超导材料反应，然后暴露于氟。氟可以是气体或等离子体的组分，或者它可以是界面层的组分。通过加热（例如，<350℃）将氟驱入a-Si或冲击以钝化诸如悬挂键的缺陷。

6. 发明申请

US20150179913A1 Fluorine Passivation of Dielectric for Superconducting Electronics 有权
标题翻译：超导电子介质的氟钝化
公开(公告)号：US20150179913A1
公开(公告)日：2015-06-25
申请号：US14137320
申请日：2013-12-20
申请人： Intermolecular, Inc.
发明人： Dipankar Pramanik , Andrew Steinbach
IPC分类号： H01L39/24 , C23C14/14 , C23C14/58 , H01L39/12
CPC分类号： C23C14/5806 , C23C14/14 , C23C14/16 , C23C14/5846 , H01L21/02123 , H01L21/02266 , H01L21/02321 , H01L21/02337 , H01L21/0234 , H01L21/3115 , H01L21/76826 , H01L21/76891 , H01L23/53285 , H01L23/5329 , H01L27/18 , H01L2924/0002 , Y10T428/265 , H01L2924/00
摘要： An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (
摘要翻译：制造用于超导电子器件的非晶硅（a-Si）电介质，通过在整个整个层中的氟钝化降低损耗角正切。通过在低温（<350℃，例如〜200℃）下的物理气相沉积形成a-Si的完整层或更薄的子层，以防止与超导材料反应，然后暴露于氟。氟可以是气体或等离子体的组分，或者它可以是界面层的组分。通过加热（例如，<350℃）将氟驱入a-Si或冲击以钝化诸如悬挂键的缺陷。

7. 发明申请

US20060197193A1 Superconductor wires for back end interconnects 有权
标题翻译：用于后端互连的超导线
公开(公告)号：US20060197193A1
公开(公告)日：2006-09-07
申请号：US11072158
申请日：2005-03-04
申请人： Shiqun Gu , Wai Lo , Hong Lin
发明人： Shiqun Gu , Wai Lo , Hong Lin
IPC分类号： H01L39/00
CPC分类号： H01L21/76838 , H01L21/76834 , H01L23/53285 , H01L2924/0002 , H01L2924/00
摘要： An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide. The superconducting material is in some embodiments at least one of an organic compound such as a potassium doped buckminsterfullerene, a cesium doped buckminsterfullerene, and other carbon containing compounds, a metallic material such as an inter-metallic material like Nb—Ti alloys and other substances formed by alloying metals, and an inorganic compound such as YBa2Cu3O7-x, (Pb,Bi)2Sr2Ca2Cu3O10-x and its derivatives, HgBaCaCuO and its derivatives, and TI—Ba—Ca—Cu—O and its derivatives.
摘要翻译：对由超导材料形成的导电互连的集成电路的改进。以这种方式，可以使导电互连非常小，但仍然具有足够的导电性。在各种实施例中，所有导电互连由超导材料形成。在一些实施例中，导电互连由各种不同的超导材料形成。在一个实施例中，只有后端导电互连由超导材料形成。在一些实施例中，没有由超导材料形成通孔。互导体电介质层优选由氧化硅形成，并且有时所有的互导电介质层均由氧化硅形成。在一些实施方案中，超导材料是有机化合物，例如掺杂钾的巴克敏斯特富勒烯，掺杂铯的德克敏斯特富勒烯和其它含碳化合物中的至少一种，金属材料如诸如Nb-Ti合金的金属间材料和其它物质由金属合金化而形成的无机化合物，例如YBa 2 N 3 O 7-x X，（Pb，Bi）2 Sr 2 O 2和其衍生物HgBaCaCuO及其衍生物和TI-Ba-Ca-Cu-O及其衍生物。

8. 发明授权

US5760463A Superconducting layer in contact with group III-V semiconductor layer for wiring structure 失效
标题翻译：与导体结构III-V族半导体层接触的超导层
公开(公告)号：US5760463A
公开(公告)日：1998-06-02
申请号：US601646
申请日：1996-02-14
申请人： Tsunehiro Hato
发明人： Tsunehiro Hato
IPC分类号： H01L39/06 , H01L23/498 , H01L23/532 , H01L23/538 , H01L39/22 , H01L39/00 , H01L29/06 , H01P1/00 , H04B1/00
CPC分类号： H01L23/498 , H01L23/49888 , H01L23/53285 , H01L23/538 , H01L2924/0002 , Y10S505/703 , Y10S505/704 , Y10S505/813 , Y10S505/856 , Y10S505/866
摘要： A superconductor device which includes a first wiring part and a second wiring part which together form a superconductive wiring. The first wiring part is arranged onto a substrate and is made of a superconductor material. The second wiring part is made of a non-oxide semiconductor material. The second wiring part is adjacent to the first wiring part and jointly forms a superconductive wiring with the first wiring part by becoming at least partly superconductive due to proximity effect with the first wiring part. The second wiring part has a smaller penetration length of magnetic field than that for the first wiring part. This structure enhances the propagation velocity of a signal within the superconductive wiring.
摘要翻译：一种超导体装置，其包括一起形成超导布线的第一布线部和第二布线部。第一布线部分布置在基板上并且由超导体材料制成。第二配线部由非氧化物半导体材料制成。第二布线部分与第一布线部分相邻，并且由于与第一布线部分的接近效应，通过变得至少部分地超导而与第一布线部分共同形成超导布线。第二配线部分具有比第一配线部分更小的磁场穿透长度。这种结构增强了超导布线内信号的传播速度。

9. 发明授权

US5700715A Process for mounting a semiconductor device to a circuit substrate 失效
标题翻译：将半导体器件安装到电路基板的工艺
公开(公告)号：US5700715A
公开(公告)日：1997-12-23
申请号：US434276
申请日：1995-05-03
申请人： Nicholas F. Pasch
发明人： Nicholas F. Pasch
IPC分类号： H01L21/60 , H01L23/532 , H01L21/283 , H01L21/58
CPC分类号： H01L24/81 , H01L23/53285 , H01L2224/10135 , H01L2224/10165 , H01L2224/81136 , H01L2224/81139 , H01L2224/8114 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/3025
摘要： A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.
摘要翻译：用于将一个或多个模具安装在基板上的方法，例如通过球凸块。在一个实施例中，诸如金的薄层的热反射材料设置在面对基板的模具的表面上，以屏蔽基板免受由模具产生的热量。其他实施例涉及形成在管芯和/或衬底的表面上的“柱”间隔件，以控制它们之间的间隔。支柱可以是导热的或热不导电的。导热柱可以通过绝缘层与管芯或衬底热隔离。可以使用导热柱将热量从模具的选定区域提取到基板的选定的线或区域中，然后基板上的热量可以被冷却剂消散。通过裸片通常加热的衬底上的线可用于限制半导体管芯上所选电路的电流。

10. 发明授权

US5659201A High conductivity interconnection line 失效
标题翻译：高导电性互连线
公开(公告)号：US5659201A
公开(公告)日：1997-08-19
申请号：US463805
申请日：1995-06-05
申请人： Donald L. Wollesen
发明人： Donald L. Wollesen
IPC分类号： H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/5283 , H01L23/53233 , H01L23/53238 , H01L23/53285 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/45124 , H01L2224/48463 , H01L2224/48699 , H01L2224/48724 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/14
摘要： High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above the wire bonding layer.
摘要翻译：高导电性互连线由诸如铜的高导电性材料形成，使用不受铜原子扩散的阻挡层。通过形成在引线接合层上方的导电互连线，优选铜互连线获得较高的工作速度。

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