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    • 23. 发明授权
    • Logic process DRAM
    • 逻辑处理DRAM
    • US06947324B1
    • 2005-09-20
    • US10734060
    • 2003-12-12
    • Winston LeePeter LeeSehat Sutardja
    • Winston LeePeter LeeSehat Sutardja
    • G11C7/18G11C11/24G11C11/4097H01L21/8242H01L27/02
    • G11C11/4097G11C7/18H01L27/0207H01L27/10885Y10S257/908
    • A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.
    • 提供了包括具有提高的信噪比,降低的位线电容和减小的面积的动态随机存取存储器(DRAM)单元的半导体集成电路器件。 DRAM单元包括多个位线对,每个位线对包括第一金属导体和第二金属导体。 每个位线对包括参考位线和感测位线。 每个位线对可以被配置为使得参考位线和感测位线相对于彼此纵向定向。 或者,每个位线对被配置为使得第一金属导体和第二金属导体在至少一个位置上彼此对称地扭曲。 单元板和晶体管栅极之间的横向间隔最小化,导致总面积减小。