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21. 发明授权

US07160777B2 Split-gate nonvolatile memory device and method of manufacturing the same 有权
标题翻译：分离式非易失性存储器件及其制造方法
公开(公告)号：US07160777B2
公开(公告)日：2007-01-09
申请号：US10916670
申请日：2004-08-11
申请人： Yong-Suk Choi , Seung-Beom Yoon
发明人： Yong-Suk Choi , Seung-Beom Yoon
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7886 , H01L29/7887
摘要： Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate insulating layer and separated apart from each other, the floating gate and the dummy pattern having round surfaces that face outward; a pair of insulating spacers, which are formed on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; a control gate formed in a self-aligned manner between the pair of insulating spacers; a tunnel insulating layer interposed between the floating gate and the control gate; and source and drain regions formed in the semiconductor substrate outside the floating gate and the dummy pattern.
摘要翻译：本发明的实施例包括形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上并且彼此分开的间隔物型浮栅和间隔物型图案，浮栅和虚设图案具有面向外的圆形表面; 一对绝缘间隔物，其形成在浮动栅极的侧壁和虚设图案的彼此面对的侧壁上; 在所述一对绝缘间隔件之间以自对准的方式形成的控制栅极; 插入在所述浮动栅极和所述控制栅极之间的隧道绝缘层; 以及在浮置栅极外部的半导体衬底和虚拟图案中形成的源极和漏极区域。

22. 发明申请

US20060244014A1 Nonvolatile memory device and method of forming same 审中-公开
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20060244014A1
公开(公告)日：2006-11-02
申请号：US11476006
申请日：2006-06-28
申请人： Yong-Suk Choi
发明人： Yong-Suk Choi
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/11568 , H01L27/115
摘要： In a method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, a plurality of first gates may be formed on a semiconductor substrate. A plurality of charge storage spacers may be formed on the plurality of first gates so that a given charge storage spacer may be disposed on a sidewall of a given first gate. A plurality of second gates may be disposed on the plurality of first gates so that a given second gate is on a sidewall of a given first gate and covers a given charge storage spacer.
摘要翻译：在形成氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器件的方法中，可以在半导体衬底上形成多个第一栅极。多个电荷存储间隔物可以形成在多个第一栅极上，使得给定的电荷存储间隔物可以设置在给定的第一栅极的侧壁上。多个第二栅极可以设置在多个第一栅极上，使得给定的第二栅极位于给定的第一栅极的侧壁上并且覆盖给定的电荷存储间隔物。

23. 发明申请

US20060199336A1 Split gate non-volatile memory devices and methods of forming same 失效
标题翻译：分闸非易失性存储器件及其形成方法
公开(公告)号：US20060199336A1
公开(公告)日：2006-09-07
申请号：US11368247
申请日：2006-03-03
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

24. 发明授权

US07091090B2 Nonvolatile memory device and method of forming same 有权
公开(公告)号：US07091090B2
公开(公告)日：2006-08-15
申请号：US10761250
申请日：2004-01-22
申请人： Yong-Suk Choi
发明人： Yong-Suk Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： In a method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, a plurality of first gates may be formed on a semiconductor substrate. A plurality of charge storage spacers may be formed on the plurality of first gates so that a given charge storage spacer may be disposed on a sidewall of a given first gate. A plurality of second gates may be disposed on the plurality of first gates so that a given second gate is on a sidewall of a given first gate and covers a given charge storage spacer.

25. 发明申请

US20050106816A1 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20050106816A1
公开(公告)日：2005-05-19
申请号：US10987340
申请日：2004-11-12
申请人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
发明人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.
摘要翻译：隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。这些层依次构图。通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

26. 发明申请

US20050051836A1 Split-gate nonvolatile memory device and method of manufacturing the same 有权
标题翻译：分离式非易失性存储器件及其制造方法
公开(公告)号：US20050051836A1
公开(公告)日：2005-03-10
申请号：US10916670
申请日：2004-08-11
申请人： Yong-Suk Choi , Seung-Beom Yoon
发明人： Yong-Suk Choi , Seung-Beom Yoon
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7886 , H01L29/7887
摘要： Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate insulating layer and separated apart from each other, the floating gate and the dummy pattern having round surfaces that face outward; a pair of insulating spacers, which are formed on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; a control gate formed in a self-aligned manner between the pair of insulating spacers; a tunnel insulating layer interposed between the floating gate and the control gate; and source and drain regions formed in the semiconductor substrate outside the floating gate and the dummy pattern.
摘要翻译：本发明的实施例包括形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上并且彼此分开的间隔物型浮栅和间隔物型图案，浮栅和虚设图案具有面向外的圆形表面; 一对绝缘间隔物，其形成在浮动栅极的侧壁和虚设图案的彼此面对的侧壁上; 在所述一对绝缘间隔件之间以自对准的方式形成的控制栅极; 插入在所述浮动栅极和所述控制栅极之间的隧道绝缘层; 以及在浮置栅极外部的半导体衬底和虚拟图案中形成的源极和漏极区域。

27. 发明授权

US06847078B2 Non-volatile memory device and method of forming the same 失效
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US06847078B2
公开(公告)日：2005-01-25
申请号：US10458133
申请日：2003-06-10
申请人： Yong-Suk Choi , Og-Hyun Lee
发明人： Yong-Suk Choi , Og-Hyun Lee
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328
摘要： A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.
摘要翻译：非易失性存储器件包括设置在半导体衬底的预定区域中的有源区，与有源区交叉的选择栅电极和布置在与选择栅电极平行的有源区上的浮置栅电极，选择栅电极。非易失性存储器件还包括介于有源区与选择栅电极和浮栅之间的隧道绝缘层，介于选择栅极和浮栅之间的分离绝缘图案，擦除栅电极设置在浮置栅电极之上并与平行于选择栅电极的有源区交叉，以及介于擦除栅电极和浮栅之间的擦除栅极绝缘层。选择栅电极形成为没有光致抗蚀剂图案。

28. 发明授权

US06793789B2 Reference electrode with a polymeric reference electrode membrane 失效
标题翻译：具有聚合物参比电极膜的参比电极
公开(公告)号：US06793789B2
公开(公告)日：2004-09-21
申请号：US09960432
申请日：2001-09-22
申请人： Yong Suk Choi , Sung Dong Lee , Seong Hee Oh , Hyo Lin Lee , Jae Ho Shin , Jeonghan Ha , Hakhyun Nam , Geun Sig Cha
发明人： Yong Suk Choi , Sung Dong Lee , Seong Hee Oh , Hyo Lin Lee , Jae Ho Shin , Jeonghan Ha , Hakhyun Nam , Geun Sig Cha
IPC分类号： G01N2731
CPC分类号： G01N27/301
摘要： Disclosed is a polymeric reference electrode membrane comprising (a) one selected from a porous polymer or a hydrophilic plasticizer; (b) a lipophilic polymer; and optionally an adhesion-enhancing material. A reference electrode equipped with the polymeric reference electrode membrane can be shortened the preconditioning time, and extended lifetime for storage and use owing to excellent adhesion, and showed reproducibility and good yield. So, a miniaturized multi-potentiometric sensor can be fabricated comprising a solid-state reference electrode of the present invention and a set of ion-selective electrodes, thus being useful in the potentiometric fields, including clinical, environmental, food and industrial analysis.
摘要翻译：公开了一种聚合物参比电极膜，其包含（a）选自多孔聚合物或亲水性增塑剂中的一种; （b）亲脂性聚合物; 和任选的粘附增强材料。配备有聚合物参比电极膜的参比电极可以缩短预处理时间，并且由于优异的粘附性而延长存储和使用寿命，并且显示出重现性和良好的产率。因此，可以制造包括本发明的固态参考电极和一组离子选择性电极的小型化多电位传感器，因此可用于电位计领域，包括临床，环境，食品和工业分析。

29. 发明申请

US20140264538A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140264538A1
公开(公告)日：2014-09-18
申请号：US14200274
申请日：2014-03-07
申请人： Tea-Kwang YU , Bae-Seong KWON , Yong-Tae KIM , Chul-Ho CHUNG , Yong-Suk CHOI
发明人： Tea-Kwang YU , Bae-Seong KWON , Yong-Tae KIM , Chul-Ho CHUNG , Yong-Suk CHOI
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L29/66
CPC分类号： H01L21/823462 , H01L21/823456 , H01L27/11546 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.
摘要翻译：在制造半导体器件的方法中，在包括单元区域和逻辑区域的衬底的单元区域上形成分离栅极结构。逻辑区域具有高电压区域，超高压区域和低电压区域，并且分离栅极结构包括第一栅极绝缘层图案，浮动栅极，隧道绝缘层图案和控制栅极。在分离栅极结构和衬底上形成间隔层。蚀刻间隔层以在分离栅极结构的侧壁上形成间隔物，并在衬底的超高电压区域上形成第二栅极绝缘层图案。在基板的高电压区域，第二栅极绝缘层图案和基板的低电压区域中的每一个上形成栅电极。

30. 发明申请

US20100103744A1 Non-volatile memory device and method of driving the same 审中-公开
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US20100103744A1
公开(公告)日：2010-04-29
申请号：US12588680
申请日：2009-10-23
申请人： Seung-jin Yang , Jeong-uk Han , Yong-tae Kim , Yong-suk Choi , Bae-seong Kwon
发明人： Seung-jin Yang , Jeong-uk Han , Yong-tae Kim , Yong-suk Choi , Bae-seong Kwon
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0433
摘要： A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors.
摘要翻译：一种非易失性存储器件包括具有以矩阵模式布置的多个单元存储单元的存储单元阵列，每个单元存储单元具有共享公共源的第一和第二非易失性存储器晶体管，以及连接在公共源和第一和第二非易失性存储器晶体管中的一个，耦合到以存储单元阵列的列方向布置的第一非易失性存储器晶体管的控制栅极的第一字线，耦合到控制的第二字线布置在存储单元阵列的列方向上的第二非易失性存储晶体管的栅极，耦合到沿着存储单元阵列的列方向布置的所选晶体管的栅极的选择线以及耦合到漏极的至少一个位线的第一和第二非易失性存储器晶体管。

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