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21. 发明授权

US07401186B2 System and method for tracking changes in L1 data cache directory 有权
标题翻译：用于跟踪L1数据缓存目录中的更改的系统和方法
公开(公告)号：US07401186B2
公开(公告)日：2008-07-15
申请号：US11054273
申请日：2005-02-09
申请人： Sheldon B. Levenstein , Anthony Saporito
发明人： Sheldon B. Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

22. 发明授权

US07380062B2 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权
标题翻译：机制在多线程微处理器中维护最佳情况需求指令重新分配
公开(公告)号：US07380062B2
公开(公告)日：2008-05-27
申请号：US11055818
申请日：2005-02-11
申请人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译：一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。检查需求缺失的高速缓存行以确定关键部门。一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

23. 发明授权

US07350051B2 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream 有权
标题翻译：从页表条目优化有效页码到实际页码转换路径的方法匹配恢复执行流
公开(公告)号：US07350051B2
公开(公告)日：2008-03-25
申请号：US11054277
申请日：2005-02-09
申请人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
发明人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
IPC分类号： G06F12/10 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

24. 发明授权

US07284094B2 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权
标题翻译：允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中获取请求同时运行，而不管其一致等级
公开(公告)号：US07284094B2
公开(公告)日：2007-10-16
申请号：US11054293
申请日：2005-02-09
申请人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译：一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。确定这些识别的未完成的有效提取条目使用的SetID。所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。

25. 发明授权

US5751990A Abridged virtual address cache directory 失效
标题翻译：简化的虚拟地址缓存目录
公开(公告)号：US5751990A
公开(公告)日：1998-05-12
申请号：US233654
申请日：1994-04-26
申请人： David John Krolak , Lyle Edwin Grosbach , Sheldon B. Levenstein , John David Irish
发明人： David John Krolak , Lyle Edwin Grosbach , Sheldon B. Levenstein , John David Irish
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1063
摘要： A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.
摘要翻译：分层存储器利用翻译后备缓冲器来快速恢复虚拟到真实的地址映射和缓存系统。缓存中的行通过指向转换后备缓冲区中的条目的缓存目录中标识。这消除了缓存目录中虚拟和实际地址的高速缓存行的冗余清单，允许目录体积小。在由处理单元进行存储器访问时，生成高速缓存散列地址以访问转换后备缓冲器条目，允许将存储在TLB条目中的地址与存储器访问的地址进行比较。一致意味着一击。同时，缓存散列地址指示缓存目录中的指针。指针应对应于缓存哈希地址，以指示缓存目录命中。发生高速缓存命中的地方。

26. 发明授权

US08549235B2 Method for detecting address match in a deeply pipelined processor design 有权
标题翻译：在深层流水线处理器设计中检测地址匹配的方法
公开(公告)号：US08549235B2
公开(公告)日：2013-10-01
申请号：US13297199
申请日：2011-11-15
申请人： Miles Robert Dooley , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B Levenstein
发明人： Miles Robert Dooley , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B Levenstein
IPC分类号： G06F12/00
CPC分类号： G06F11/362
摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.
摘要翻译：一种用于以可以使用处理器的关键区域中的最小物理空间来实现的深度流水线处理器设计中的地址匹配的快速检测的方法，装置和算法。地址比较分为两部分。第一部分是快速部分地址匹配比较系统。第二部分是较慢的全地址匹配比较系统。如果检测到请求的地址和注册表地址之间的部分匹配，则在执行完整的地址匹配检查时暂时停止执行请求地址的程序或指令集。如果完整的地址匹配检查导致所请求的地址和注册表地址之间的完全匹配，则程序或指令集被中断和停止。否则，程序或指令集继续执行。

27. 发明授权

US07831775B2 System and method for tracking changes in L1 data cache directory 有权
标题翻译：用于跟踪L1数据缓存目录中的更改的系统和方法
公开(公告)号：US07831775B2
公开(公告)日：2010-11-09
申请号：US12131432
申请日：2008-06-02
申请人： Sheldon B. Levenstein , Anthony Saporito
发明人： Sheldon B. Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

28. 发明授权

US07809924B2 System for generating effective address 有权
标题翻译：用于生成有效地址的系统
公开(公告)号：US07809924B2
公开(公告)日：2010-10-05
申请号：US12048527
申请日：2008-03-14
申请人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
发明人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译：用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分多个有效地址的有效地址位。通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

29. 发明授权

US07788450B2 Method and apparatus for efficiently accessing both aligned and unaligned data from a memory 有权
标题翻译：用于从存储器有效地访问对准和未对齐数据的方法和装置
公开(公告)号：US07788450B2
公开(公告)日：2010-08-31
申请号：US11837241
申请日：2007-08-10
申请人： Eric Jason Fluhr , Sheldon B. Levenstein
发明人： Eric Jason Fluhr , Sheldon B. Levenstein
IPC分类号： G06F12/06
CPC分类号： G06F12/04 , G06F12/0846 , G06F12/0886
摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.
摘要翻译：一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

30. 发明申请

US20080209177A1 Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch 有权
标题翻译：多线程微处理器中维护最佳案例需求指令重新分配的机制
公开(公告)号：US20080209177A1
公开(公告)日：2008-08-28
申请号：US12113561
申请日：2008-05-01
申请人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译：一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。检查需求缺失的高速缓存行以确定关键部门。一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

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