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1. 发明授权

US5751990A Abridged virtual address cache directory 失效
标题翻译：简化的虚拟地址缓存目录
公开(公告)号：US5751990A
公开(公告)日：1998-05-12
申请号：US233654
申请日：1994-04-26
申请人： David John Krolak , Lyle Edwin Grosbach , Sheldon B. Levenstein , John David Irish
发明人： David John Krolak , Lyle Edwin Grosbach , Sheldon B. Levenstein , John David Irish
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1063
摘要： A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.
摘要翻译：分层存储器利用翻译后备缓冲器来快速恢复虚拟到真实的地址映射和缓存系统。缓存中的行通过指向转换后备缓冲区中的条目的缓存目录中标识。这消除了缓存目录中虚拟和实际地址的高速缓存行的冗余清单，允许目录体积小。在由处理单元进行存储器访问时，生成高速缓存散列地址以访问转换后备缓冲器条目，允许将存储在TLB条目中的地址与存储器访问的地址进行比较。一致意味着一击。同时，缓存散列地址指示缓存目录中的指针。指针应对应于缓存哈希地址，以指示缓存目录命中。发生高速缓存命中的地方。

2. 发明授权

US5790838A Pipelined memory interface and method for using the same 失效
标题翻译：流水线存储器接口及其使用方法
公开(公告)号：US5790838A
公开(公告)日：1998-08-04
申请号：US700263
申请日：1996-08-20
申请人： John David Irish , Charles Luther Johnson , David John Krolak , Sheldon Bernard Levenstein
发明人： John David Irish , Charles Luther Johnson , David John Krolak , Sheldon Bernard Levenstein
IPC分类号： G11C7/10 , G06F1/04
CPC分类号： G11C7/1039 , G11C7/1072
摘要： According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.
摘要翻译：根据本发明，公开了流水线SRAM结构和计时方法。 SRAM接口和时钟方法专门用于2级和3级缓存SRAM存储器件。在本发明中，生成用于CPU的时钟信号的振荡器也用于生成与SRAM接口的所有其它组件的时钟信号。每个生成的时钟信号都取决于相同的时钟事件，允许降低时钟速度以进行测试或调试，同时保持更高速度的时钟边缘关系。从振荡器产生的各种时钟信号用于从多个周期循环窃取时间。这种技术允许5纳秒（nS）访问访问次数大于5 nS的2级和3级高速缓存存储器设备。

3. 发明授权

US6151664A Programmable SRAM and DRAM cache interface with preset access priorities 有权
标题翻译：可编程SRAM和DRAM缓存接口，具有预设的访问优先级
公开(公告)号：US6151664A
公开(公告)日：2000-11-21
申请号：US329134
申请日：1999-06-09
申请人： John Michael Borkenhagen , Gerald Gregory Fagerness , John David Irish , David John Krolak
发明人： John Michael Borkenhagen , Gerald Gregory Fagerness , John David Irish , David John Krolak
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08 , G06F13/18
CPC分类号： G06F12/0893
摘要： A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on the processor and one portion on the cache. A designer can simply select which RAM he or she wishes to use for a cache, and the cache controller interface portion on the processor configures the processor to use this type of RAM. The cache interface portion on the cache is simple when being used with DRAM in that a busy indication is asserted so that the processor knows when an access collision occurs between an access generated by the processor and the DRAM cache. An access collision occurs when the DRAM cache is unable to read or write data due to a precharge, initialization, refresh, or standby state. When the cache interface is used with an SRAM cache, the busy indication is preferably ignored by a processor and the processor's cache interface portion. Additionally, the disclosed cache interface allows speed and size requirements for the cache to be programmed into the interface. In this manner, the interface does not have to be redesigned for use with different sizes or speeds of caches.
摘要翻译：公开了一种支持静态随机存取存储器（SRAM）和动态随机存取存储器（DRAM）的缓存接口。高速缓存接口优选地包括两个部分，处理器上的一个部分和高速缓存上的一个部分。设计人员可以简单地选择他或她希望用于高速缓存的RAM，并且处理器上的高速缓存控制器接口部分使处理器使用这种类型的RAM。当与DRAM一起使用时，缓存上的高速缓存接口部分是简单的，因为忙指示被断言，使得处理器知道在由处理器生成的访问与DRAM高速缓存之间何时发生访问冲突。当DRAM高速缓存由于预充电，初始化，刷新或待机状态而无法读取或写入数据时，发生访问冲突。当高速缓存接口与SRAM缓存一起使用时，处理器和处理器的高速缓存接口部分最好忽略忙指示。此外，所公开的高速缓存接口允许高速缓存的速度和大小要求被编程到接口中。以这种方式，界面不必重新设计用于不同大小或速度的高速缓存。

4. 发明授权

US08792332B2 Implementing lane shuffle for fault-tolerant communication links 有权
标题翻译：实施容错通信链路的车道洗牌
公开(公告)号：US08792332B2
公开(公告)日：2014-07-29
申请号：US12884389
申请日：2010-09-17
申请人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
发明人： Ryan Abel Heckendorf , Kerry Christopher Imming , John David Irish , Ibrahim Abdel-Rahman Ouda
IPC分类号： H04L12/26 , H04W24/08 , H04W24/00 , H04W28/04
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译：一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。移位模板通过由失败掩码控制的一组移位器进行级联。

5. 发明授权

US07961732B2 Method and hardware apparatus for implementing frame alteration commands 失效
标题翻译：用于实现帧改变命令的方法和硬件设备
公开(公告)号：US07961732B2
公开(公告)日：2011-06-14
申请号：US12044998
申请日：2008-03-09
申请人： John David Irish , Ibrahim Abdel-Rahman Ouda , James A. Steenburgh , Jason Andrew Thompson
发明人： John David Irish , Ibrahim Abdel-Rahman Ouda , James A. Steenburgh , Jason Andrew Thompson
IPC分类号： H04L12/28 , G06F15/167 , G06F15/173
CPC分类号： H04L69/12
摘要： A method and apparatus are provided for implementing frame alteration commands in a communications network processor. A set of frame alteration instruction templates is defined. A frame alteration instruction template is identified based upon the packet type recognition result of a received packet. A frame alteration instruction stream is generated utilizing the frame alteration instruction template. Each of the frame alteration instruction templates includes different frame alteration commands to be performed on a packet. Pointers to indirect data bytes to be inserted in a packet are stored in the frame alteration instruction templates. The generated frame alteration instruction stream is used by hardware to provide frame alterations.
摘要翻译：提供了一种用于在通信网络处理器中实现帧改变命令的方法和装置。定义了一组帧改变指令模板。基于接收到的分组的分组类型识别结果来识别帧改变指令模板。使用帧改变指令模板生成帧改变指令流。每个帧改变指令模板包括要在分组上执行的不同帧改变命令。要插入数据包的间接数据字节的指针存储在帧改变指令模板中。生成的帧改变指令流被硬件用于提供帧改变。

6. 发明授权

US07382777B2 Method for implementing actions based on packet classification and lookup results 有权
标题翻译：基于分组分类和查找结果实现动作的方法
公开(公告)号：US07382777B2
公开(公告)日：2008-06-03
申请号：US10463288
申请日：2003-06-17
申请人： John David Irish , Ibrahim Abdel-Rahman Ouda , James A. Steenburgh , Jason Andrew Thompson
发明人： John David Irish , Ibrahim Abdel-Rahman Ouda , James A. Steenburgh , Jason Andrew Thompson
IPC分类号： H04L12/56 , G06F12/00 , G06F15/173
CPC分类号： H04L47/10 , H04L47/2408 , H04L47/2441
摘要： A method and apparatus are provided for implementing predefined actions based upon packet classification and lookup results in a communications network processor. A plurality of sets of rules is defined. Each rule set includes at least one rule and each rule has a set of masked compares for comparing results of hits and misses of table lookups. Each masked compare set has an associated field for selecting an action. The action defines a set of one or more commands and each command defines a processing operation. One rule set is identified based upon the packet classification result for a received packet. When one of the rules is identified having a match of the masked compares, then the action of associated with the identified rule is selected. Otherwise a default action is provided responsive to no rule of the identified rule set having a match of the masked compares.
摘要翻译：提供了一种基于通信网络处理器中的分组分类和查找结果来实现预定动作的方法和装置。定义了多组规则。每个规则集包括至少一个规则，每个规则具有一组掩码的比较，用于比较表查找的命中和未命中的结果。每个被屏蔽的比较集合都有一个关联的字段用于选择一个动作。该动作定义一组一个或多个命令，每个命令定义一个处理操作。基于接收到的分组的分组分类结果来识别一个规则集。当识别出其中一个规则具有被掩蔽的比较的匹配时，则选择与所识别的规则相关联的动作。否则，响应于不具有所掩蔽的比较的匹配的所识别的规则集的规则来提供默认动作。

7. 发明授权

US08170024B2 Implementing pointer and stake model for frame alteration code in a network processor 失效
标题翻译：在网络处理器中实现帧更改代码的指针和投注模型
公开(公告)号：US08170024B2
公开(公告)日：2012-05-01
申请号：US11934810
申请日：2007-11-05
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。为选择用于发送的分组提供当前指针和分支。保持当前指针用于跟踪分组中帧更改操作的当前位置。保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。高级指针指令允许当前和指针指针以任意数量的字节进入数据包。

8. 发明授权

US07917700B2 Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state 失效
标题翻译：使用替代PLRU算法和受害者缓存一致性状态替换高速缓存行的方法和缓存控制电路
公开(公告)号：US07917700B2
公开(公告)日：2011-03-29
申请号：US11924163
申请日：2007-10-25
申请人： John David Irish , Chad B. McBride , Jack Chris Randolph
发明人： John David Irish , Chad B. McBride , Jack Chris Randolph
IPC分类号： G06F12/12
CPC分类号： G06F12/122 , G06F12/128
摘要： A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.
摘要翻译：一种用于使用具有受害者高速缓存一致性状态的替代伪最近最少使用（PLRU）算法来替换高速缓存行的方法和高速缓存控制电路，以及设置有对象高速缓存控制电路所在的设计结构。当识别到同余类中的替换要求时，计算用于替换的第一PLRU高速缓存行和用于替换的替代PLRU高速缓存行。当用于替换的第一PLRU高速缓存行处于受害者高速缓存一致性状态时，替代的PLRU高速缓存行被选择使用。

9. 发明授权

US07634591B2 Method and apparatus for tracking command order dependencies 失效
标题翻译：跟踪命令顺序相关性的方法和装置
公开(公告)号：US07634591B2
公开(公告)日：2009-12-15
申请号：US11340736
申请日：2006-01-26
申请人： John David Irish , Chad B. McBride
发明人： John David Irish , Chad B. McBride
IPC分类号： G06F3/00 , G06F9/30
CPC分类号： G06F9/3838
摘要： Methods and apparatus for tracking dependencies of commands to be executed by a command processor are provided. By determining the dependency of incoming commands against all commands awaiting execution, dependency information can be stored in a dependency scoreboard. Such a dependency scoreboard may be used to determine if a command is ready to be issued by the command processor. The dependency scoreboard can also be updated with information relating to the issuance of commands, for example, as commands complete.
摘要翻译：提供了用于跟踪由命令处理器执行的命令的依赖性的方法和装置。通过确定输入命令对所有等待执行的命令的依赖性，依赖性信息可以存储在依赖记分板中。可以使用这种依赖记分板来确定命令处理器是否准备好发出命令。还可以使用与命令发布相关的信息来更新依赖记分板，例如，完成命令。

10. 发明申请

US20080198853A1 APPARATUS FOR IMPLEMENTING ACTIONS BASED ON PACKET CLASSIFICATION AND LOOKUP RESULTS 审中-公开
标题翻译：基于分组分类和查询结果执行操作的设备
公开(公告)号：US20080198853A1
公开(公告)日：2008-08-21
申请号：US12106365
申请日：2008-04-21
申请人： John David Irish , Ibrahim Abdel-Rahman Ouda , James A. Steenburgh , Jason Andrew Thompson
发明人： John David Irish , Ibrahim Abdel-Rahman Ouda , James A. Steenburgh , Jason Andrew Thompson
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/2408 , H04L47/2441
摘要： A method and apparatus are provided for implementing predefined actions based upon packet classification and lookup results in a communications network processor. A plurality of sets of rules is defined. Each rule set includes at least one rule and each rule has a set of masked compares for comparing results of hits and misses of table lookups. Each masked compare set has an associated field for selecting an action. The action defines a set of one or more commands and each command defines a processing operation. One rule set is identified based upon the packet classification result for a received packet. When one of the rules is identified having a match of the masked compares, then the action of associated with the identified rule is selected. Otherwise a default action is provided responsive to no rule of the identified rule set having a match of the masked compares.
摘要翻译：提供了一种基于通信网络处理器中的分组分类和查找结果来实现预定动作的方法和装置。定义了多组规则。每个规则集包括至少一个规则，每个规则具有一组掩码的比较，用于比较表查找的命中和未命中的结果。每个被屏蔽的比较集合都有一个关联的字段用于选择一个动作。该动作定义一组一个或多个命令，每个命令定义一个处理操作。基于接收到的分组的分组分类结果来识别一个规则集。当识别出其中一个规则具有被掩蔽的比较的匹配时，则选择与所识别的规则相关联的动作。否则，响应于不具有所掩蔽的比较的匹配的所识别的规则集的规则来提供默认动作。

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