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21. 发明授权

US08397144B1 BCH data correction system and method 有权
标题翻译： BCH数据校正系统及方法
公开(公告)号：US08397144B1
公开(公告)日：2013-03-12
申请号：US12913716
申请日：2010-10-27
申请人： Christopher I. W. Norrie , Alessia Marelli , Rino Micheloni , Peter Z. Onufryk
发明人： Christopher I. W. Norrie , Alessia Marelli , Rino Micheloni , Peter Z. Onufryk
IPC分类号： H03M13/00
CPC分类号： H03M13/6566 , H03M13/152 , H03M13/1555 , H03M13/6561
摘要： In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.
摘要翻译：在各种实施例中，数据校正系统具有包括搜索模块的数据路径。每个搜索模块具有用于基于定位多项式定位数据单元中的多个数据位错误的相应位错误容量。数据校正系统基于输入数据单元产生校正子，根据校正子产生定位多项式，并根据定位多项式确定输入数据单元中的数据位错误数。此外，数据校正系统选择搜索模块中的一个具有至少输入数据单元中的数据位错误数量的位错误容量。所选择的搜索模块基于定位多项式生成错误指示符。数据校正系统根据误差指示器校正输入数据单元中的每个数据位错误。

22. 发明申请

US20110167318A1 READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE AND MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE 有权
标题翻译：具有嵌入式错误修正代码的存储器件和带有嵌入式错误校正代码的存储器件的读取方法
公开(公告)号：US20110167318A1
公开(公告)日：2011-07-07
申请号：US13047678
申请日：2011-03-14
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并且生成至少一个第二恢复串（S2-SN）。基于第一恢复串（S1）与第二恢复串恢复字符串（S2-SN），生成修改字符串（SM），其中存在擦除（X），并且使用修改字符串（SM）执行至少一个第二解码尝试。

23. 发明申请

US20110167206A1 CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE 有权
标题翻译：多级闪存存储器件的配置
公开(公告)号：US20110167206A1
公开(公告)日：2011-07-07
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F12/02
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

24. 发明申请

US20090262593A1 CIRCUIT AND METHOD FOR RETRIEVING DATA STORED IN SEMICONDUCTOR MEMORY CELLS 有权
标题翻译：用于检测存储在半导体存储器单元中的数据的电路和方法
公开(公告)号：US20090262593A1
公开(公告)日：2009-10-22
申请号：US12248843
申请日：2008-10-09
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04 , G11C16/06 , G11C5/14
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

25. 发明授权

US07474577B2 Circuit and method for retrieving data stored in semiconductor memory cells 有权
标题翻译：用于检索存储在半导体存储单元中的数据的电路和方法
公开(公告)号：US07474577B2
公开(公告)日：2009-01-06
申请号：US11444892
申请日：2006-05-31
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

26. 发明授权

US07394694B2 Flash memory device with NAND architecture with reduced capacitive coupling effect 有权
标题翻译：具有NAND架构的闪存器件具有降低的电容耦合效应
公开(公告)号：US07394694B2
公开(公告)日：2008-07-01
申请号：US11445491
申请日：2006-05-31
申请人： Rino Micheloni , Roberto Ravasio , Ilaria Motta
发明人： Rino Micheloni , Roberto Ravasio , Ilaria Motta
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.
摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。恢复逻辑相对于超过读取参考值的限制值读取每个组，仅对至少一个单元的阈值电压没有达到极限值的每个组进行编程，并且响应于达到极限值而停止恢复至少一组这些组。

27. 发明授权

US07382660B2 Method for accessing a multilevel nonvolatile memory device of the flash NAND type 有权
标题翻译：用于访问闪存NAND型的多级非易失性存储器件的方法
公开(公告)号：US07382660B2
公开(公告)日：2008-06-03
申请号：US11458904
申请日：2006-07-20
申请人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
发明人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5641
摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
摘要翻译：多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。第一位的编程确定从第一阈值电平转换到第二阈值电平。第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

28. 发明申请

US20080123411A1 Page buffer for multi-level NAND electrically-programmable semiconductor memories 有权
标题翻译：多级NAND电可编程半导体存储器的页缓冲器
公开(公告)号：US20080123411A1
公开(公告)日：2008-05-29
申请号：US11821131
申请日：2007-06-21
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C7/1021 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3459 , G11C2211/5621
摘要： A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential. The programming state change enabling means comprises reading means for retrieving, from the selected memory cell, an indication of an existing data value already stored in the second group of data bits, receiving means for receiving an indication of a target data value to be stored in the first group of data bits of the selected memory cell, combining means activatable during a combining phase for combining the indication of the existing data value with the indication of the received target data value, so as to obtain a modified indication corresponding to a target programming state for the memory cell and conditioning means for causing a potential of the coupling line to take the program enabling potential or the program inhibition potential depending on the modified indication. The combining means includes a coupling electrical path between the reading means and the receiving means, said coupling electrical line being kept isolated from the coupling electrical path during said combining phase.
摘要翻译：提供了用于电可编程存储器的页面缓冲器。页面缓冲器包括多个存储器单元，对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储器单元中的数据位数N> = 2，其中数据位至少包括第一数据位组和第二数据位组以及至少一个具有与所选存储单元可操作地相关联的耦合线的读/写单元。读取/编程单元适于至少临时存储从或将被写入所选择的存储单元中的数据位，并且包括编程状态改变使能装置，用于通过使所述耦合线选择性地启用所选存储单元的编程状态的改变在一个能够实现潜力和程序禁止潜力的程序中。编程状态改变使能装置包括读取装置，用于从所选择的存储器单元检索已经存储在第二组数据位中的现有数据值的指示，接收装置，用于接收要存储的目标数据值的指示所选择的存储器单元的第一组数据位，在组合阶段可激活的组合装置，用于组合现有数据值的指示与接收到的目标数据值的指示，以便获得对应于目标编程的修改指示用于存储单元的状态和调节装置，用于使耦合线的电位取决于经修改的指示使能电位或程序禁止电位。组合装置包括在读取装置和接收装置之间的耦合电路，所述耦合电线在所述组合阶段期间与耦合电路保持隔离。

29. 发明申请

US20070053227A1 High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
标题翻译：非挥发性浮栅存储器具有低输出纹波的高压开关
公开(公告)号：US20070053227A1
公开(公告)日：2007-03-08
申请号：US11437405
申请日：2006-05-19
申请人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
发明人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C5/14
CPC分类号： H02M3/073 , G11C5/145 , G11C8/08 , G11C16/08 , G11C16/12 , H02M2003/077 , H03K3/356104 , H03K17/063 , H03K17/6872 , H03K17/6874
摘要： A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
摘要翻译：高压开关具有高电压输入端子，接收高电压和输出端子。具有控制端子的传输晶体管连接在高电压输入端子和输出端子之间。电荷泵型的倍压电路的输出端与控制端子连接。电压倍增电路是对称型的，具有第一和第二电荷存储装置，接收周期型的时钟信号，并且具有第一电路支路和第二电路支路，它们彼此对称并在相对于时钟信号的相位相反。

30. 发明授权

US07184348B2 Sensing circuit for a semiconductor memory 有权
标题翻译：半导体存储器的感应电路
公开(公告)号：US07184348B2
公开(公告)日：2007-02-27
申请号：US11194739
申请日：2005-08-01
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C7/12 , G11C16/24 , G11C16/28
摘要： A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one comparator. The first circuit branch is coupled to a memory cell to be sensed so as to be run through by a current corresponding to a memory cell state. The feedback-controlled circuit element controls a memory cell access voltage, and the current-to-voltage conversion circuit converts the current into a corresponding converted voltage signal that is indicative of the memory cell state. The comparator compares the converted voltage signal with a comparison voltage for discriminating among at least two different states of the memory cell. The converted voltage signal corresponds to a control signal of the feedback-controlled circuit element. Also provided is a method of sensing a memory cell.
摘要翻译：提供感测电路用于感测半导体存储单元。感测电路包括至少一个第一电路支路，第一电路支路中的反馈控制电路元件，第一支路中的电流 - 电压转换电路和至少一个比较器。第一电路分支耦合到待感测的存储器单元，以便通过对应于存储单元状态的电流运行。反馈控制电路元件控制存储单元访问电压，并且电流 - 电压转换电路将电流转换成指示存储单元状态的对应的转换电压信号。比较器将转换的电压信号与比较电压进行比较，以便在存储单元的至少两个不同状态之间进行区分。转换后的电压信号对应于反馈控制电路元件的控制信号。还提供了一种感测存储器单元的方法。

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