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1. 发明授权

US07382660B2 Method for accessing a multilevel nonvolatile memory device of the flash NAND type 有权
标题翻译：用于访问闪存NAND型的多级非易失性存储器件的方法
公开(公告)号：US07382660B2
公开(公告)日：2008-06-03
申请号：US11458904
申请日：2006-07-20
申请人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
发明人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5641
摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
摘要翻译：多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。第一位的编程确定从第一阈值电平转换到第二阈值电平。第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

2. 发明申请

US20070047299A1 METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE FLASH NAND TYPE 有权
标题翻译：用于访问闪存NAND类型的多个非易失性存储器件的方法
公开(公告)号：US20070047299A1
公开(公告)日：2007-03-01
申请号：US11458904
申请日：2006-07-20
申请人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
发明人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5641
摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
摘要翻译：多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。第一位的编程确定从第一阈值电平转换到第二阈值电平。第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

3. 发明申请

US20060059406A1 Memory with embedded error correction codes 有权
公开(公告)号：US20060059406A1
公开(公告)日：2006-03-16
申请号：US11221584
申请日：2005-09-08
申请人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
发明人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

4. 发明授权

US07581153B2 Memory with embedded error correction codes 有权
标题翻译：具有嵌入式纠错码的内存
公开(公告)号：US07581153B2
公开(公告)日：2009-08-25
申请号：US11221584
申请日：2005-09-08
申请人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
发明人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.
摘要翻译：内存有一条总线用于数据，地址和命令。数据寄存器耦合到总线以存储写入存储器和从存储器读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到总线以寻址存储器。存储器还包括用于计算ECC的纠错码电路。存储器被配置为响应于用于控制ECC电路的操作的外部命令，用于读取或写入与控制存储器数据的读取或写入的外部命令分离的ECC。存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。

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