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21. 发明授权

US06335274B1 Method for forming a high-RI oxide film to reduce fluorine diffusion in HDP FSG process 有权
标题翻译：用于形成高RI氧化膜以减少HDP FSG工艺中的氟扩散的方法
公开(公告)号：US06335274B1
公开(公告)日：2002-01-01
申请号：US09714128
申请日：2000-11-17
申请人： Shu-Li Wu , Pei-Ren Jeng
发明人： Shu-Li Wu , Pei-Ren Jeng
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/02304 , H01L21/31612 , H01L21/31629 , H01L21/76834
摘要： A method for forming a high-RI dielectric liner layer to prevent out diffusion of fluorine substances in an intermetal dielectric (IMD) layer of an semiconductor device is provided. The method comprises following steps. First, a patterned conductive layer is deposited on a substrate. Then, a dielectric liner layer is formed by high density plasma enhanced chemical vapor deposition method or plasma enhanced chemical vapor deposition method. The dielectric liner layer is silicon dioxide and has a high-RI between about 1.5 to 1.8. Next, a fluorinated silicate glass layer is deposited on the dielectric liner layer. The high-RI dielectric liner layer is used to reduce out diffusion of fluorine substances in the fluorinated silicate glass layer. Last, it is proceeded a chemical mechanism polishing process to remove additional fluorinated silicate glass layer and the dielectric liner layer.
摘要翻译：提供了形成高RI电介质衬垫层以防止氟物质在半导体器件的金属间电介质（IMD）层中的扩散的方法。该方法包括以下步骤。首先，将图案化的导电层沉积在衬底上。然后，通过高密度等离子体增强化学气相沉积法或等离子体增强化学气相沉积法形成电介质衬垫层。电介质衬垫层是二氧化硅，并且具有在约1.5至1.8之间的高RI。接下来，氟化硅酸盐玻璃层沉积在电介质衬垫层上。高RI介电衬垫层用于减少氟化硅酸盐玻璃层中氟物质的扩散。最后，进行化学机构抛光工艺以除去附加的氟化硅酸盐玻璃层和介电衬里层。

22. 发明授权

US5877074A Method for improving the electrical property of gate in polycide structure 失效
标题翻译：改善多晶硅结构栅极电性能的方法
公开(公告)号：US5877074A
公开(公告)日：1999-03-02
申请号：US998958
申请日：1997-12-29
申请人： Pei-Ren Jeng , Chun-Cho Chen
发明人： Pei-Ren Jeng , Chun-Cho Chen
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28061
摘要： A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.
摘要翻译：公开了一种改善多晶硅结构中栅极电性能的方法。首先，在硅衬底的表面上形成栅氧化层。以下步骤用作本发明的关键点之一，其包括以下步骤：（1）在栅极氧化物上形成高度掺杂的多晶硅层，（2）在多晶硅层上形成未掺杂的非晶硅层，（3）在非晶硅上形成钨硅层。接下来，进行高温退火和短时间退火。这种堆叠栅极结构具有低电阻并且可以解决以下问题：（1）退火后硅化钨的剥离，（2）由于来自硅化钨的氟原子的扩散和渗透导致的栅极电性能的劣化。

23. 发明授权

US09337059B2 Apparatus and methods for annealing wafers 有权
标题翻译：用于退火晶圆的设备和方法
公开(公告)号：US09337059B2
公开(公告)日：2016-05-10
申请号：US13215909
申请日：2011-08-23
申请人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/00 , H01L21/324 , H01L21/268 , H01L21/20 , H01L21/36 , H01L21/44
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
摘要翻译：一种方法包括在晶片上进行退火。晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。

24. 发明申请

US20130122676A1 SOURCE/DRAIN DOPING METHOD IN 3D DEVICES 有权
标题翻译： 3D设备中的源/排水方法
公开(公告)号：US20130122676A1
公开(公告)日：2013-05-16
申请号：US13293679
申请日：2011-11-10
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L21/225 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0847 , H01L29/66636 , H01L29/66803 , H01L29/7834
摘要： The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first type from the doping layer into the substrate. This can form a doped region that may be the source/drain extension of the 3D device. An epitaxial region is then grown in the recess. The epitaxial region can form the source/drain region of the 3D device.
摘要翻译：本公开提供了用于3D设备的半导体器件制造的方法。一种方法包括提供具有凹陷并在衬底上和凹部中形成掺杂层的衬底。然后将衬底退火。退火将掺杂层中的第一类掺杂剂驱动到衬底中。这可以形成可以是3D器件的源/漏扩展的掺杂区域。然后在凹槽中生长外延区域。外延区域可以形成3D器件的源极/漏极区域。

25. 发明授权

US08404561B2 Method for fabricating an isolation structure 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US08404561B2
公开(公告)日：2013-03-26
申请号：US12774219
申请日：2010-05-05
申请人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
发明人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232
摘要： The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
摘要翻译：本发明涉及集成电路制造，更具体地说涉及具有几乎没有空隙的隔离结构的电子器件。一种用于制造隔离结构的示例性方法，包括：提供衬底; 在衬底中形成沟槽; 用第一氧化硅部分地填充沟槽; 将第一氧化硅的表面暴露于包含NH 3和含氟化合物的蒸汽混合物中; 将基板加热至100℃至200℃的温度; 并用第二氧化硅填充沟槽，由此所制成的隔离结构几乎没有空隙。

26. 发明授权

US07880213B2 Bottom electrode of metal-insulator-metal capacitor 有权
标题翻译：金属 - 绝缘体 - 金属电容器底部电极
公开(公告)号：US07880213B2
公开(公告)日：2011-02-01
申请号：US11308841
申请日：2006-05-15
申请人： Wen-Miao Lo , Lurng-Sheng Lee , Pei-Ren Jeng , Cha-Hsin Lin , Ching-Chiun Wang
发明人： Wen-Miao Lo , Lurng-Sheng Lee , Pei-Ren Jeng , Cha-Hsin Lin , Ching-Chiun Wang
IPC分类号： H01L27/108
CPC分类号： H01L21/0337 , H01L28/65
摘要： A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.
摘要翻译：提供一种制造金属 - 绝缘体 - 金属（MIM）电容器的底部电极的结构和方法。首先，在基板上形成过渡金属层。此后，在过渡金属层上形成具有纳米图案的自组装聚合物膜，以暴露过渡金属层的一部分。使用自组装聚合物膜作为掩模，过渡金属层的暴露部分被处理以进行相变，使得底部电极可以实现纳米级的相分离。此后，去除自组装聚合物膜。

27. 发明授权

US07723226B2 Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
标题翻译：包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例
公开(公告)号：US07723226B2
公开(公告)日：2010-05-25
申请号：US11654427
申请日：2007-01-17
申请人： Chen-Hua Yu , Yung-Cheng Lu , Pei-Ren Jeng , Chia-Cheng Chou , Keng-Chu Lin , Chung-Chi Ko , Tien-I Bao , Shwang-Ming Jeng
发明人： Chen-Hua Yu , Yung-Cheng Lu , Pei-Ren Jeng , Chia-Cheng Chou , Keng-Chu Lin , Chung-Chi Ko , Tien-I Bao , Shwang-Ming Jeng
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76835 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.
摘要翻译：提出了双层多孔低介电常数（低k）互连结构及其制造方法。具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。底层和顶层具有相同的原子组成，但是较高的介电常数值k。底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

28. 发明授权

US07446038B2 Interlayer interconnect of three-dimensional memory and method for manufacturing the same 有权
标题翻译：三维存储器的层间互连及其制造方法
公开(公告)号：US07446038B2
公开(公告)日：2008-11-04
申请号：US11423619
申请日：2006-06-12
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L21/302
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/085
摘要： An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs.
摘要翻译：三维存储器的层间互连结构包括存储单元组，每个存储单元组由多个存储单元组成，并且由于线和第一插头的特殊布置以及线路布局而连接到它们各自的选择晶体管。线路布局涉及在多个水平平面中的每一个上布置多个线，并且在布置在上部和下部水平水平的相邻线之间选择性地形成第二插塞，使得插头选择性地将相邻的上部和下部线路相互连接。由于在设置在三维存储器中的堆叠层的各个堆叠状态中采用相同的布局图案，所以三维存储器的堆叠层的上层和下层共享相同的布局，导致数量的减少使用的面罩，更简单的工艺调整和更低的成本。

29. 发明授权

US07157360B2 Memory device and method for forming a passivation layer thereon 有权
标题翻译：用于在其上形成钝化层的存储器件和方法
公开(公告)号：US07157360B2
公开(公告)日：2007-01-02
申请号：US10671773
申请日：2003-09-29
申请人： Hung-Yu Chiu , U-Way Tseng , Wen-Pin Lu , Cheng-Chen Huseh , Pei-Ren Jeng , Fu-Hsiang Hsu
发明人： Hung-Yu Chiu , U-Way Tseng , Wen-Pin Lu , Cheng-Chen Huseh , Pei-Ren Jeng , Fu-Hsiang Hsu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L23/3192 , H01L23/291 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.
摘要翻译：具有改善的钝化结构的存储器件。存储器件包括其上具有存储器单元的半导体衬底，在半导体衬底的表面上的与存储器单元连接的互连结构，以及在互连结构的表面上的钝化结构。钝化结构包括在互连结构的表面上的电介质层和介电层表面上的氧 - 氮化硅（SiOxNy）层。

30. 发明授权

US07151042B2 Method of improving flash memory performance 有权
标题翻译：提高闪存性能的方法
公开(公告)号：US07151042B2
公开(公告)日：2006-12-19
申请号：US11049230
申请日：2005-02-02
申请人： Pei-Ren Jeng , Hsuan-Ling Kao
发明人： Pei-Ren Jeng , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L21/28273 , H01L29/66825
摘要： A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).
摘要翻译：一种提高闪存性能的方法。该方法包括：提供其上具有栅极结构的衬底，栅极结构具有栅极电介质层，第一多晶硅层，工作介电层和第二多晶硅层; 然后，沉积栅极绝缘层以封闭栅极结构，用于形成侧壁间隔物; 接下来，在衬底和封闭的栅极结构上进行第一退火; 然后，通过使用包含氧O 2和氮气N 2的混合气体的稀释氧化方法在衬底和封闭的栅极结构上进行电池再氧化。本发明减少了interoly介电层和隧道氧化物中的侵蚀问题，并提高了栅极耦合比（GCR）。

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